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<H2><![section=4]>D. Using the Verga Simulator in Stand-Alone Mode</H2>
While Verga was written to support use through the TkGate graphical
interface, it is possible to use Verga by itself in stand-alone mode.
The input files need not be TkGate generated Verilog, and can be
arbitrary Verilog code, as long as it uses only the subset of
constructs supported by Verga.
<p>
To invoke Verga, use a command of the form:
<p>
<tt style="padding-left: 20;">verga</tt><i>[options] [files]</i>
<p>
The supported options are:
<p>
<table class=display>
<tr><th width=75 align=left>Option</th><th align=left>Description</th></tr>
<tr><td colspan=2><hr></td></tr>
<tr><td><tt>-i</tt></td><td class=wide><b>Interactive mode</b> - In
this mode, Verga will continue to read from the standard input while
the simulation is running to accept commands controlling the
simulation. This is the mode that the TkGate GUI uses when invoking
Verga, and is generally only useful to TkGate.</td></tr>
<tr><td><tt>-e</tt></td><td class=wide><b>List error messages</b> - Dump a list of all the error messages that Verga can generate.</td></tr>
<tr><td><tt>-l</tt></td><td class=wide><b>Show License</b> - Print out the license information to the screen.</td></tr>
<tr><td><tt>-S</tt> <i>script</i></td><td class=wide><b>Load
Script</b> - Load a simulation script on start-up. This switch can be
specified multiple times to load multiple scripts.</td></tr>
<tr><td><tt>-W</tt> <i>mode</i></td><td class=wide><b>Warning Mode</b>
- Sets the warning mode indicating how warnings are to be treated.
<i>Mode</i> is a numeric value between 1 and 4. If <i>mode</i> is 1,
warning will be ignored. If <i>mode</i> is 2, warnings will be
reported only if there are errors. If <i>mode</i> is 3, warnings will
always be reports. If <i>mode</i> is 4, warnings will be treated as
errors, and the simulator will not start if there are warnings. The
default <i>mode</i> value is 3.</td></tr>
<tr><td><tt>-s</tt></td><td class=wide><b>Scan Mode</b> - Scans the
modules in the input file and reports the names of the modules, and
the variables declared in them. No simulation is performed.</td></tr>
<tr><td><tt>-q</tt></td><td class=wide><b>Quite Mode</b> - Suppress
printing of unnecessary messages.</td></tr>
<tr><td><tt>-P</tt></td><td class=wide><b>Print Modules</b> - Echos
back the input file from the internal parsed data.</td></tr>
<tr><td><tt>-B</tt> <i>dir</i></td><td class=wide><b>Base Directory</b> - Makes <i>dir</i> the default directory when searching for files.</td></tr>
<tr><td><tt>-t</tt> <i>name</i></td><td class=wide><b>Set Top
Module</b> - Makes <i>name</i> the top-level module rather than
automatically selecting one.</td></tr> <tr><td><tt>-d</tt>
<i>type</i></td><td class=wide><b>Delay Type</b> - Sets the delay
values to use. <i>type</i> can be one of <tt>min</tt>, <tt>max</tt>
or <tt>typical</tt>.</td></tr>
</table>
<p>
Verga will scan all Verilog files specified on the command line. If
the <tt>-t</tt> switch is not used to specify the top-level module,
Verga will assume that the first module with no ports is the top-level
module. Any output generated by the simulation is printed to the
screen.
<p>
If you are using Verga to simulate a file saved from TkGate, you must
be sure that you have enabled "Include cells in save files" from the
<a href="gateOptions.html#general">General Options</a> dialog box. If
you do not, Verga will be unable to find the definitions for TkGate's
built-in devices.
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