/usr/share/doc/covered/TODO is in covered 0.7.10-3+b1.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 | The following items are known to be problems in the current code that need to be fixed
or features that are unimplemented/not complete that need to be done.
Legend
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X = This feature/fix has been completed and tested
IP = In Progress
Build process
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Score command
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1. Add ability for user to specify FSM all possible states/state transitions
for a particular FSM on a command-line basis.
2. Add ability to automatically extract all possible states/state transitions
for a specified FSM.
3. Add ability to automatically locate and extract an FSM from the design
without user intervention.
4. Add more Verilog-2001 constructs to parser.
- config command
5. Allow Covered to run simulation phases in parallel to increase performance.
6. Add feature to cause Covered to omit the simulation phase for toggle and
FSM coverage results.
7. Add SystemVerilog features/syntax
IP - typedef
IP - struct
IP - union
IP - enum
8. Have Covered have the ability to generate XML CDD files.
X 9. Enhance the -rI option to allow the user to ignore certain types of race conditions.
10. Add a configure option to allow the user to set the size of the vector ulong typedef
to their own preference.
Merge command
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Report command
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1. Provide additional information in toggle coverage regarding port (interface) coverage.
Rank command
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GUI
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Documentation
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Miscellaneous
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IP 1. Add regression that produces known, achievable error conditions in the code.
IP 2. Make all code splint clean.
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