This file is indexed.

/usr/share/faumachine/experiments/test-vt102/user-begin.vhdl is in faumachine-data 20110812-1.2.

This file is owned by root:root, with mode 0o644.

The actual contents of the file can be viewed below.

  1
  2
  3
  4
  5
  6
  7
  8
  9
 10
 11
 12
 13
 14
 15
 16
 17
 18
 19
 20
 21
 22
 23
 24
 25
 26
 27
 28
 29
 30
 31
 32
 33
 34
 35
 36
 37
 38
 39
 40
 41
 42
 43
 44
 45
 46
 47
 48
 49
 50
 51
 52
 53
 54
 55
 56
 57
 58
 59
 60
 61
 62
 63
 64
 65
 66
 67
 68
 69
 70
 71
 72
 73
 74
 75
 76
 77
 78
 79
 80
 81
 82
 83
 84
 85
 86
 87
 88
 89
 90
 91
 92
 93
 94
 95
 96
 97
 98
 99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
-- $Id: user-begin.vhdl,v 1.4 2009-08-25 06:29:16 sand Exp $
--
-- Copyright (C) 2007-2009 FAUmachine Team <info@faumachine.org>.
--
-- This program is free software. You can redistribute it and/or modify it
-- under the terms of the GNU General Public License, either version 2 of
-- the License, or (at your option) any later version. See COPYING.

library expect;
use expect.types.all;
use expect.procedures.all;
library ieee;
use ieee.std_logic_1164.ALL;

entity user is
	port(
		term0_power_switch : out boolean;
		term0_key : out boolean_array(0 to 127);
		term0_screen_shot : out boolean;
		term0_rec : out boolean;
		term0_opt_screen : in opt_rgb;

		term1_power_switch : out boolean;
		term1_key : out boolean_array(0 to 127);
		term1_screen_shot : out boolean;
		term1_rec : out boolean;
		term1_opt_screen : in opt_rgb
	);
end user;

architecture behaviour of user is
	signal pm0_int_text0 : cstring;
	signal pm0_int_text1 : cstring;
	signal pm0_int_text2 : cstring;
	signal pm0_int_text3 : cstring;
	signal pm0_int_text0_state : boolean;
	signal pm0_int_text1_state : boolean;
	signal pm0_int_text2_state : boolean;
	signal pm0_int_text3_state : boolean;
	signal pm0_int_slot0 : match;
	signal pm0_int_slot1 : match;
	signal pm0_int_slot2 : match;
	signal pm0_int_slot3 : match;
	signal pm0_int_slot4 : match;
	signal pm0_int_slot5 : match;
	signal pm0_int_slot6 : match;
	signal pm0_int_slot7 : match;
	signal pm0_int_slot8 : match;
	signal pm0_int_slot9 : match;
	signal pm0_int_slot10 : match;
	signal pm0_int_slot11 : match;
	signal pm0_int_slot12 : match;
	signal pm0_int_slot13 : match;
	signal pm0_int_slot14 : match;
	signal pm0_int_slot15 : match;
	signal pm0_int_rectangle0 : cstring;
	signal pm0_int_rectangle1 : cstring;
	signal pm0_int_rectangle2 : cstring;
	signal pm0_int_rectangle3 : cstring;

	signal pm1_int_text0 : cstring;
	signal pm1_int_text1 : cstring;
	signal pm1_int_text2 : cstring;
	signal pm1_int_text3 : cstring;
	signal pm1_int_text0_state : boolean;
	signal pm1_int_text1_state : boolean;
	signal pm1_int_text2_state : boolean;
	signal pm1_int_text3_state : boolean;
	signal pm1_int_slot0 : match;
	signal pm1_int_slot1 : match;
	signal pm1_int_slot2 : match;
	signal pm1_int_slot3 : match;
	signal pm1_int_slot4 : match;
	signal pm1_int_slot5 : match;
	signal pm1_int_slot6 : match;
	signal pm1_int_slot7 : match;
	signal pm1_int_slot8 : match;
	signal pm1_int_slot9 : match;
	signal pm1_int_slot10 : match;
	signal pm1_int_slot11 : match;
	signal pm1_int_slot12 : match;
	signal pm1_int_slot13 : match;
	signal pm1_int_slot14 : match;
	signal pm1_int_slot15 : match;
	signal pm1_int_rectangle0 : cstring;
	signal pm1_int_rectangle1 : cstring;
	signal pm1_int_rectangle2 : cstring;
	signal pm1_int_rectangle3 : cstring;


	signal t0_int_asc_text0 : cstring;
	signal t0_int_asc_text1 : cstring;
	signal t0_int_asc_text2 : cstring;
	signal t0_int_asc_text3 : cstring;
	signal t0_int_asc_text0_state : boolean;
	signal t0_int_asc_text1_state : boolean;
	signal t0_int_asc_text2_state : boolean;
	signal t0_int_asc_text3_state : boolean;

	signal t1_int_asc_text0 : cstring;
	signal t1_int_asc_text1 : cstring;
	signal t1_int_asc_text2 : cstring;
	signal t1_int_asc_text3 : cstring;
	signal t1_int_asc_text0_state : boolean;
	signal t1_int_asc_text1_state : boolean;
	signal t1_int_asc_text2_state : boolean;
	signal t1_int_asc_text3_state : boolean;


begin
	patternmatcher0 : patternm 
		port map (
			video => term0_opt_screen,
			text0 => pm0_int_text0,
			text0_state => pm0_int_text0_state,
			text1 => pm0_int_text1, 
			text1_state => pm0_int_text1_state,
			text2 => pm0_int_text2,
			text2_state => pm0_int_text2_state,
			text3 => pm0_int_text3, 
			text3_state => pm0_int_text3_state,
			asc_text0 => t0_int_asc_text0,
			asc_text0_state => t0_int_asc_text0_state,
			asc_text1 => t0_int_asc_text1, 
			asc_text1_state => t0_int_asc_text1_state,
			asc_text2 => t0_int_asc_text2,
			asc_text2_state => t0_int_asc_text2_state,
			asc_text3 => t0_int_asc_text3, 
			asc_text3_state => t0_int_asc_text3_state,
			slot0 => pm0_int_slot0,
			slot1 => pm0_int_slot1,
			slot2 => pm0_int_slot2,
			slot3 => pm0_int_slot3,
			slot4 => pm0_int_slot4,
			slot5 => pm0_int_slot5,
			slot6 => pm0_int_slot6,
			slot7 => pm0_int_slot7,
			slot8 => pm0_int_slot8,
			slot9 => pm0_int_slot9,
			slot10 => pm0_int_slot10,
			slot11 => pm0_int_slot11,
			slot12 => pm0_int_slot12,
			slot13 => pm0_int_slot13,
			slot14 => pm0_int_slot14,
			slot15 => pm0_int_slot15,
			pattern_rectangle0 => pm0_int_rectangle0,
			pattern_rectangle1 => pm0_int_rectangle1,
			pattern_rectangle2 => pm0_int_rectangle2,
			pattern_rectangle3 => pm0_int_rectangle3
		);

	patternmatcher1 : patternm 
		port map (
			video => term1_opt_screen,
			text0 => pm1_int_text0,
			text0_state => pm1_int_text0_state,
			text1 => pm1_int_text1, 
			text1_state => pm1_int_text1_state,
			text2 => pm1_int_text2,
			text2_state => pm1_int_text2_state,
			text3 => pm1_int_text3, 
			text3_state => pm1_int_text3_state,
			asc_text0 => t1_int_asc_text0,
			asc_text0_state => t1_int_asc_text0_state,
			asc_text1 => t1_int_asc_text1, 
			asc_text1_state => t1_int_asc_text1_state,
			asc_text2 => t1_int_asc_text2,
			asc_text2_state => t1_int_asc_text2_state,
			asc_text3 => t1_int_asc_text3, 
			asc_text3_state => t1_int_asc_text3_state,
			slot0 => pm1_int_slot0,
			slot1 => pm1_int_slot1,
			slot2 => pm1_int_slot2,
			slot3 => pm1_int_slot3,
			slot4 => pm1_int_slot4,
			slot5 => pm1_int_slot5,
			slot6 => pm1_int_slot6,
			slot7 => pm1_int_slot7,
			slot8 => pm1_int_slot8,
			slot9 => pm1_int_slot9,
			slot10 => pm1_int_slot10,
			slot11 => pm1_int_slot11,
			slot12 => pm1_int_slot12,
			slot13 => pm1_int_slot13,
			slot14 => pm1_int_slot14,
			slot15 => pm1_int_slot15,
			pattern_rectangle0 => pm1_int_rectangle0,
			pattern_rectangle1 => pm1_int_rectangle1,
			pattern_rectangle2 => pm1_int_rectangle2,
			pattern_rectangle3 => pm1_int_rectangle3
		);


	installation_script : process
	begin