/usr/include/llvm-3.9/llvm/CodeGen/MachineCombinerPattern.h is in llvm-3.9-dev 1:3.9.1-19ubuntu1.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 | //===-- llvm/CodeGen/MachineCombinerPattern.h - Instruction pattern supported by
// combiner ------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines instruction pattern supported by combiner
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
#define LLVM_CODEGEN_MACHINECOMBINERPATTERN_H
namespace llvm {
/// These are instruction patterns matched by the machine combiner pass.
enum class MachineCombinerPattern {
// These are commutative variants for reassociating a computation chain. See
// the comments before getMachineCombinerPatterns() in TargetInstrInfo.cpp.
REASSOC_AX_BY,
REASSOC_AX_YB,
REASSOC_XA_BY,
REASSOC_XA_YB,
// These are multiply-add patterns matched by the AArch64 machine combiner.
MULADDW_OP1,
MULADDW_OP2,
MULSUBW_OP1,
MULSUBW_OP2,
MULADDWI_OP1,
MULSUBWI_OP1,
MULADDX_OP1,
MULADDX_OP2,
MULSUBX_OP1,
MULSUBX_OP2,
MULADDXI_OP1,
MULSUBXI_OP1,
// Floating Point
FMULADDS_OP1,
FMULADDS_OP2,
FMULSUBS_OP1,
FMULSUBS_OP2,
FMULADDD_OP1,
FMULADDD_OP2,
FMULSUBD_OP1,
FMULSUBD_OP2,
FMLAv1i32_indexed_OP1,
FMLAv1i32_indexed_OP2,
FMLAv1i64_indexed_OP1,
FMLAv1i64_indexed_OP2,
FMLAv2f32_OP2,
FMLAv2f32_OP1,
FMLAv2f64_OP1,
FMLAv2f64_OP2,
FMLAv2i32_indexed_OP1,
FMLAv2i32_indexed_OP2,
FMLAv2i64_indexed_OP1,
FMLAv2i64_indexed_OP2,
FMLAv4f32_OP1,
FMLAv4f32_OP2,
FMLAv4i32_indexed_OP1,
FMLAv4i32_indexed_OP2,
FMLSv1i32_indexed_OP2,
FMLSv1i64_indexed_OP2,
FMLSv2i32_indexed_OP2,
FMLSv2i64_indexed_OP2,
FMLSv2f32_OP2,
FMLSv2f64_OP2,
FMLSv4i32_indexed_OP2,
FMLSv4f32_OP2
};
} // end namespace llvm
#endif
|