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<a name="Terminal-Mode-Commands"></a>
<div class="header">
<p>
Next: <a href="Terminal-Mode-Examples.html#Terminal-Mode-Examples" accesskey="n" rel="next">Terminal Mode Examples</a>, Previous: <a href="Terminal-Mode-Operation.html#Terminal-Mode-Operation" accesskey="p" rel="prev">Terminal Mode Operation</a>, Up: <a href="Terminal-Mode-Operation.html#Terminal-Mode-Operation" accesskey="u" rel="up">Terminal Mode Operation</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>]</p>
</div>
<hr>
<a name="Terminal-Mode-Commands-1"></a>
<h3 class="section">3.1 Terminal Mode Commands</h3>

<p>The following commands are implemented:
</p>
<dl compact="compact">
<dt><code>dump <var>memtype</var> <var>addr</var> <var>nbytes</var></code></dt>
<dd><p>Read <var>nbytes</var> from the specified memory area, and display them in
the usual hexadecimal and ASCII form.
</p>
</dd>
<dt><code>dump</code></dt>
<dd><p>Continue dumping the memory contents for another <var>nbytes</var> where the
previous dump command left off.
</p>
</dd>
<dt><code>write <var>memtype</var> <var>addr</var> <var>byte1</var> &hellip; <var>byteN</var></code></dt>
<dd><p>Manually program the respective memory cells, starting at address addr,
using the values <var>byte1</var> through <var>byteN</var>.  This feature is not
implemented for bank-addressed memories such as the flash memory of
ATMega devices.
</p>
</dd>
<dt><code>erase</code></dt>
<dd><p>Perform a chip erase.
</p>
</dd>
<dt><code>send <var>b1</var> <var>b2</var> <var>b3</var> <var>b4</var></code></dt>
<dd><p>Send raw instruction codes to the AVR device.  If you need access to a
feature of an AVR part that is not directly supported by AVRDUDE, this
command allows you to use it, even though AVRDUDE does not implement the
command.   When using direct SPI mode, up to 3 bytes
can be omitted.
</p>
</dd>
<dt><code>sig</code></dt>
<dd><p>Display the device signature bytes.
</p>
</dd>
<dt><code>spi</code></dt>
<dd><p>Enter direct SPI mode.  The <em>pgmled</em> pin acts as slave select.
<em>Only supported on parallel bitbang programmers.</em>
</p>
</dd>
<dt><code>part</code></dt>
<dd><p>Display the current part settings and parameters.  Includes chip
specific information including all memory types supported by the
device, read/write timing, etc.
</p>
</dd>
<dt><code>pgm</code></dt>
<dd><p>Return to programming mode (from direct SPI mode).
</p>
</dd>
<dt><code>verbose [<var>level</var>]</code></dt>
<dd><p>Change (when <var>level</var> is provided), or display the verbosity
level.
The initial verbosity level is controlled by the number of <code>-v</code> options
given on the command line.
</p>
</dd>
<dt><code>?</code></dt>
<dt><code>help</code></dt>
<dd><p>Give a short on-line summary of the available commands.
</p>
</dd>
<dt><code>quit</code></dt>
<dd><p>Leave terminal mode and thus AVRDUDE.
</p>
</dd>
</dl>

<p>In addition, the following commands are supported on the STK500
and STK600 programmer:
</p>
<dl compact="compact">
<dt><code>vtarg <var>voltage</var></code></dt>
<dd><p>Set the target&rsquo;s supply voltage to <var>voltage</var> Volts.
</p>
</dd>
<dt><code>varef [<var>channel</var>] <var>voltage</var></code></dt>
<dd><p>Set the adjustable voltage source to <var>voltage</var> Volts.
This voltage is normally used to drive the target&rsquo;s
<em>Aref</em> input on the STK500 and STK600.
The STK600 offers two reference voltages, which can be
selected by the optional parameter <var>channel</var> (either
0 or 1).
</p>
</dd>
<dt><code>fosc <var>freq</var>[<code>M</code>|<code>k</code>]</code></dt>
<dd><p>Set the master oscillator to <var>freq</var> Hz.
An optional trailing letter <code>M</code>
multiplies by 1E6, a trailing letter <code>k</code> by 1E3.
</p>
</dd>
<dt><code>fosc off</code></dt>
<dd><p>Turn the master oscillator off.
</p>
</dd>
<dt><code>sck <var>period</var></code></dt>
<dd><p><em>STK500 and STK600 only:</em>
Set the SCK clock period to <var>period</var> microseconds.
</p>
<p><em>JTAG ICE only:</em>
Set the JTAG ICE bit clock period to <var>period</var> microseconds.
Note that unlike STK500 settings, this setting will be reverted to
its default value (approximately 1 microsecond) when the programming
software signs off from the JTAG ICE.
This parameter can also be used on the JTAG ICE mkII/3 to specify the
ISP clock period when operating the ICE in ISP mode.
</p>
</dd>
<dt><code>parms</code></dt>
<dd><p><em>STK500 and STK600 only:</em>
Display the current voltage and master oscillator parameters.
</p>
<p><em>JTAG ICE only:</em>
Display the current target supply voltage and JTAG bit clock rate/period.
</p>
</dd>
</dl>

<hr>
<div class="header">
<p>
Next: <a href="Terminal-Mode-Examples.html#Terminal-Mode-Examples" accesskey="n" rel="next">Terminal Mode Examples</a>, Previous: <a href="Terminal-Mode-Operation.html#Terminal-Mode-Operation" accesskey="p" rel="prev">Terminal Mode Operation</a>, Up: <a href="Terminal-Mode-Operation.html#Terminal-Mode-Operation" accesskey="u" rel="up">Terminal Mode Operation</a> &nbsp; [<a href="index.html#SEC_Contents" title="Table of contents" rel="contents">Contents</a>]</p>
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