/usr/src/gcc-4.8/debian/patches/gdc-versym-cpu.diff is in gcc-4.8-source 4.8.2-19ubuntu1.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 | # DP: Implements D CPU version conditions.
This implements the following versions:
* D_HardFloat
* D_SoftFloat
for all supported architectures. And these where appropriate:
* ARM
** ARM_Thumb
** ARM_HardFloat
** ARM_SoftFloat
** ARM_SoftFP
* AArch64
* Alpha
** Alpha_SoftFloat
** Alpha_HardFloat
* X86
* X86_64
** D_X32
* IA64
* MIPS32
* MIPS64
** MIPS_O32
** MIPS_O64
** MIPS_N32
** MIPS_N64
** MIPS_EABI
** MIPS_HardFloat
** MIPS_SoftFloat
* HPPA
* HPPA64
* PPC
* PPC64
** PPC_HardFloat
** PPC_SoftFloat
* S390
* S390X
* SH
* SH64
* SPARC
* SPARC64
* SPARC_V8Plus
** SPARC_HardFloat
** SPARC_SoftFloat
Index: b/src/gcc/config/aarch64/aarch64.h
===================================================================
--- a/src/gcc/config/aarch64/aarch64.h
+++ b/src/gcc/config/aarch64/aarch64.h
@@ -51,6 +51,14 @@
\
} while (0)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do \
+ { \
+ builtin_define ("AArch64"); \
+ builtin_define ("D_HardFloat"); \
+ } while (0)
+
/* Target machine storage layout. */
Index: b/src/gcc/config/alpha/alpha.h
===================================================================
--- a/src/gcc/config/alpha/alpha.h
+++ b/src/gcc/config/alpha/alpha.h
@@ -72,6 +72,23 @@
SUBTARGET_LANGUAGE_CPP_BUILTINS(); \
} while (0)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do \
+ { \
+ builtin_define ("Alpha"); \
+ if (TARGET_SOFT_FP) \
+ { \
+ builtin_define ("D_SoftFloat"); \
+ builtin_define ("Alpha_SoftFloat"); \
+ } \
+ else \
+ { \
+ builtin_define ("D_HardFloat"); \
+ builtin_define ("Alpha_HardFloat"); \
+ } \
+} while (0)
+
#ifndef SUBTARGET_LANGUAGE_CPP_BUILTINS
#define SUBTARGET_LANGUAGE_CPP_BUILTINS() \
do \
Index: b/src/gcc/config/arm/arm.h
===================================================================
--- a/src/gcc/config/arm/arm.h
+++ b/src/gcc/config/arm/arm.h
@@ -158,6 +158,31 @@
builtin_define ("__ARM_ARCH_EXT_IDIV__"); \
} while (0)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do \
+ { \
+ builtin_define ("ARM"); \
+ \
+ if (TARGET_THUMB || TARGET_THUMB2) \
+ builtin_define ("ARM_Thumb"); \
+ \
+ if (TARGET_HARD_FLOAT_ABI) \
+ builtin_define ("ARM_HardFloat"); \
+ else \
+ { \
+ if(TARGET_SOFT_FLOAT) \
+ builtin_define ("ARM_SoftFloat"); \
+ else if(TARGET_HARD_FLOAT) \
+ builtin_define ("ARM_SoftFP"); \
+ } \
+ \
+ if(TARGET_SOFT_FLOAT) \
+ builtin_define ("D_SoftFloat"); \
+ else if(TARGET_HARD_FLOAT) \
+ builtin_define ("D_HardFloat"); \
+ } while (0)
+
#include "config/arm/arm-opts.h"
enum target_cpus
Index: b/src/gcc/config/i386/i386.h
===================================================================
--- a/src/gcc/config/i386/i386.h
+++ b/src/gcc/config/i386/i386.h
@@ -588,6 +588,24 @@
/* Target CPU builtins. */
#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do { \
+ if (TARGET_64BIT) \
+ { \
+ builtin_define("X86_64"); \
+ if (TARGET_X32) \
+ builtin_define("D_X32"); \
+ } \
+ else \
+ builtin_define("X86"); \
+ \
+ if (TARGET_80387) \
+ builtin_define("D_HardFloat"); \
+ else \
+ builtin_define("D_SoftFloat"); \
+ } while (0)
+
/* Target Pragmas. */
#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()
Index: b/src/gcc/config/ia64/ia64.h
===================================================================
--- a/src/gcc/config/ia64/ia64.h
+++ b/src/gcc/config/ia64/ia64.h
@@ -40,6 +40,13 @@
builtin_define("__BIG_ENDIAN__"); \
} while (0)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+do { \
+ builtin_define ("IA64"); \
+ builtin_define ("D_HardFloat"); \
+} while (0)
+
#ifndef SUBTARGET_EXTRA_SPECS
#define SUBTARGET_EXTRA_SPECS
#endif
Index: b/src/gcc/config/mips/mips.h
===================================================================
--- a/src/gcc/config/mips/mips.h
+++ b/src/gcc/config/mips/mips.h
@@ -551,6 +551,54 @@
} \
while (0)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do \
+ { \
+ if (TARGET_64BIT) \
+ builtin_define("MIPS64"); \
+ else \
+ builtin_define("MIPS32"); \
+ \
+ switch (mips_abi) \
+ { \
+ case ABI_32: \
+ builtin_define("MIPS_O32"); \
+ break; \
+ \
+ case ABI_O64: \
+ builtin_define("MIPS_O64"); \
+ break; \
+ \
+ case ABI_N32: \
+ builtin_define("MIPS_N32"); \
+ break; \
+ \
+ case ABI_64: \
+ builtin_define("MIPS_N64"); \
+ break; \
+ \
+ case ABI_EABI: \
+ builtin_define("MIPS_EABI"); \
+ break; \
+ \
+ default: \
+ gcc_unreachable(); \
+ } \
+ \
+ if (TARGET_HARD_FLOAT_ABI) \
+ { \
+ builtin_define("MIPS_HardFloat"); \
+ builtin_define("D_HardFloat"); \
+ } \
+ else if (TARGET_SOFT_FLOAT_ABI) \
+ { \
+ builtin_define("MIPS_SoftFloat"); \
+ builtin_define("D_SoftFloat"); \
+ } \
+ } \
+ while (0)
+
/* Default target_flags if no switches are specified */
#ifndef TARGET_DEFAULT
Index: b/src/gcc/config/pa/pa.h
===================================================================
--- a/src/gcc/config/pa/pa.h
+++ b/src/gcc/config/pa/pa.h
@@ -185,6 +185,20 @@
builtin_define("_PA_RISC1_0"); \
} while (0)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+do { \
+ if(TARGET_64BIT) \
+ builtin_define("HPPA64"); \
+ else \
+ builtin_define("HPPA"); \
+ \
+ if(TARGET_SOFT_FLOAT) \
+ builtin_define ("D_SoftFloat"); \
+ else \
+ builtin_define ("D_HardFloat"); \
+} while (0)
+
/* An old set of OS defines for various BSD-like systems. */
#define TARGET_OS_CPP_BUILTINS() \
do \
Index: b/src/gcc/config/rs6000/rs6000.h
===================================================================
--- a/src/gcc/config/rs6000/rs6000.h
+++ b/src/gcc/config/rs6000/rs6000.h
@@ -613,6 +613,28 @@
#define TARGET_CPU_CPP_BUILTINS() \
rs6000_cpu_cpp_builtins (pfile)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do \
+ { \
+ if (TARGET_64BIT) \
+ builtin_define ("PPC64"); \
+ else \
+ builtin_define ("PPC"); \
+ \
+ if (TARGET_HARD_FLOAT) \
+ { \
+ builtin_define ("PPC_HardFloat"); \
+ builtin_define ("D_HardFloat"); \
+ } \
+ else if (TARGET_SOFT_FLOAT) \
+ { \
+ builtin_define ("PPC_SoftFloat"); \
+ builtin_define ("D_SoftFloat"); \
+ } \
+ } \
+ while (0)
+
/* This is used by rs6000_cpu_cpp_builtins to indicate the byte order
we're compiling for. Some configurations may need to override it. */
#define RS6000_CPU_CPP_ENDIAN_BUILTINS() \
Index: b/src/gcc/config/s390/s390.h
===================================================================
--- a/src/gcc/config/s390/s390.h
+++ b/src/gcc/config/s390/s390.h
@@ -114,6 +114,22 @@
} \
while (0)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do \
+ { \
+ if (TARGET_64BIT) \
+ builtin_define ("S390X"); \
+ else \
+ builtin_define ("S390"); \
+ \
+ if(TARGET_SOFT_FLOAT) \
+ builtin_define ("D_SoftFloat"); \
+ else if(TARGET_HARD_FLOAT) \
+ builtin_define ("D_HardFloat"); \
+ } \
+ while (0)
+
#ifdef DEFAULT_TARGET_64BIT
#define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP | MASK_OPT_HTM)
#else
Index: b/src/gcc/config/sh/sh.h
===================================================================
--- a/src/gcc/config/sh/sh.h
+++ b/src/gcc/config/sh/sh.h
@@ -31,6 +31,22 @@
#define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile)
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+ do \
+ { \
+ if (TARGET_SHMEDIA64) \
+ builtin_define ("SH64"); \
+ else \
+ builtin_define ("SH"); \
+ \
+ if (TARGET_FPU_ANY) \
+ builtin_define ("D_HardFloat"); \
+ else \
+ builtin_define ("D_SoftFloat"); \
+ } \
+ while (0)
+
/* Value should be nonzero if functions must have frame pointers.
Zero means the frame pointer need not be set up (and parms may be accessed
via the stack pointer) in functions that seem suitable. */
Index: b/src/gcc/config/sparc/sparc.h
===================================================================
--- a/src/gcc/config/sparc/sparc.h
+++ b/src/gcc/config/sparc/sparc.h
@@ -27,6 +27,31 @@
#define TARGET_CPU_CPP_BUILTINS() sparc_target_macros ()
+/* Target CPU builtins for D. */
+#define TARGET_CPU_D_BUILTINS() \
+do \
+ { \
+ if (TARGET_64BIT) \
+ builtin_define ("SPARC64"); \
+ else \
+ builtin_define ("SPARC"); \
+ \
+ if(TARGET_V8PLUS) \
+ builtin_define ("SPARC_V8Plus"); \
+ \
+ if(TARGET_FPU) \
+ { \
+ builtin_define ("D_HardFloat"); \
+ builtin_define ("SPARC_HardFloat"); \
+ } \
+ else \
+ { \
+ builtin_define ("D_SoftFloat"); \
+ builtin_define ("SPARC_SoftFloat"); \
+ } \
+ } \
+ while (0)
+
/* Specify this in a cover file to provide bi-architecture (32/64) support. */
/* #define SPARC_BI_ARCH */
|