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/usr/share/codeblocks/lexers/lexer_verilog.sample is in codeblocks-common 13.12-3.

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// D flip-flop
module d_ff ( d, clk, q, q_bar);
input d ,clk;
output q, q_bar;
wire d ,clk;
reg q, q_bar;

always @ (posedge clk)
begin
    q <= d;
    q_bar <=  ! d;
end

endmodule