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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 | <html><head><meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1"><title>Chapter 3. Coverage Boundaries</title><link rel="stylesheet" href="covered.css" type="text/css"><meta name="generator" content="DocBook XSL Stylesheets V1.71.1"><link rel="start" href="index.html" title="Covered User's Guide - 0.7.9"><link rel="up" href="part.overview.html" title="Part I. Overview"><link rel="prev" href="chapter.metrics.html" title="Chapter 2. Coverage Metrics"><link rel="next" href="chapter.race.html" title="Chapter 4. Race Condition Checking"><center><img src="img/banner.jpg"></center><hr></head><body bgcolor="#dfeef8" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">Chapter 3. Coverage Boundaries</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="chapter.metrics.html"><img src="img/prev.gif" alt="Prev"></a> </td><th width="60%" align="center">Part I. Overview</th><td width="20%" align="right"> <a accesskey="n" href="chapter.race.html"><img src="img/next.gif" alt="Next"></a></td></tr></table><hr></div><div class="chapter" lang="en"><div class="titlepage"><div><div><h2 class="title"><a name="chapter.boundaries"></a>Chapter 3. Coverage Boundaries</h2></div></div></div><div class="toc"><p><b>Table of Contents</b></p><dl><dt><span class="sect1"><a href="chapter.boundaries.html#section.boundaries.analyzed">3.1. What logic can be analyzed?</a></span></dt><dd><dl><dt><span class="sect2"><a href="chapter.boundaries.html#section.boundaries.analyzed.1995">Verilog-1995 constructs</a></span></dt><dt><span class="sect2"><a href="chapter.boundaries.html#section.boundaries.analyzed.2001">Verilog-2001 constructs</a></span></dt><dt><span class="sect2"><a href="chapter.boundaries.html#section.boundaries.analyzed.sv">SystemVerilog constructs</a></span></dt></dl></dd><dt><span class="sect1"><a href="chapter.boundaries.html#section.boundaries.unanalyzed">3.2. What logic cannot be currently analyzed?</a></span></dt><dd><dl><dt><span class="sect2"><a href="chapter.boundaries.html#section.boundaries.unanalyzed.1995">Verilog-1995 constructs</a></span></dt><dt><span class="sect2"><a href="chapter.boundaries.html#section.boundaries.unanalyzed.2001">Verilog-2001 constructs</a></span></dt></dl></dd><dt><span class="sect1"><a href="chapter.boundaries.html#section.boundaries.handling">3.3. What is done with code blocks that contain code that cannot be analyzed?</a></span></dt></dl></div><p>
To properly evaluate the effectiveness of any coverage tool, it is necessary to understand what kinds of logic are
able to be analyzed and which kinds of logic are unable to be analyzed (along with a reason for why the logic cannot
be adequately covered). Understanding the limitations of tools up front can often guide the user of those tools to
make better decisions in their usage. In the case of Covered and the open source community, it may also help drive
ideas to how to correct or get around these limitations.
</p><p>
For these reasons, a list of what type of logic can be analyzed and what type of logic cannot be currently analyzed
is listed below. Note that both of these lists may not be exhaustive and are subject to change between releases of
the tool. Also note that it is the goal of Covered to be able to parse all of the Verilog-1995, Verilog-2001, and a
subset of SystemVerilog constructs though some portions of these may be ignored for coverage purposes.
</p><div class="sect1" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="section.boundaries.analyzed"></a>3.1. What logic can be analyzed?</h2></div></div></div><div class="sect2" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="section.boundaries.analyzed.1995"></a>Verilog-1995 constructs</h3></div></div></div><p>
</p><div class="orderedlist"><ol type="1"><li><p>
All expressional logic which is comprised of the following data types and operators which exist in an assign
block, always block, initial block, task, function or named begin/end block:
</p><p>
</p><div class="itemizedlist"><ul type="disc"><li><p>Nets: <code class="code">wire, tri, tri0, tri1, wor, wand, trior, triand, supply0, suppl1</code></p></li><li><p>Triregs: <code class="code">trireg</code></p></li><li><p>Registers: <code class="code">reg</code></p></li><li><p>Parameter values</p></li><li><p>String values</p></li><li><p>Integer values</p></li><li><p>Unary operators: <code class="code">+, -, ~, &, |, ^, ~&, ~|, ~^</code></p></li><li><p>Arithmetic operators: <code class="code">+, -, *, /, %</code></p></li><li><p>Logical operators: <code class="code">&&, ||, !</code></p></li><li><p>Relational operators: <code class="code">>, <, >=, <=</code></p></li><li><p>Equality operators: <code class="code">==, ===, !=, !==</code></p></li><li><p>Bitwise operators: <code class="code">&, |, ^, ~&, ~|, ~^</code></p></li><li><p>Shift operators: <code class="code"><<, >></code></p></li><li><p>Concatentation/replication operators: <code class="code">{}, {{...}}</code></p></li><li><p>Bit select operators: <code class="code">[], [:]</code></p></li><li><p>Conditional operator: <code class="code">?:</code></p></li></ul></div><p>
</p></li><li><p>case, casex, casez statements</p></li><li><p>if, if/else statements</p></li><li><p>Delays when delay value is integer</p></li><li><p>Delayed procedural assignments (i.e., "<code class="code">a = #5 b;</code>" or "<code class="code">a = @(c) b;</code>")</p></li><li><p>Event waits and triggers: <code class="code">wait, @(posedge), @(negedge), @(), -></code></p></li><li><p>Repetition statements: <code class="code">for, while, repeat</code></p></li><li><p>Fork/join statements</p></li><li><p>Memories</p></li><li><p>$finish and $stop system calls</p></li><li><p>$time and $random system functions</p></li><li><p>Real numbers</p></li><li><p>Real number system tasks: $rtoi, $itor, $realtobits, $bitstoreal</p></li><li><p>$test$plusargs system function</p></li><li><p>
The following system tasks are allowed within logic blocks being considered for coverage:
</p><p>
$display, $dumpall, $dumpfile, $dumpflush, $dumplimit, $dumpvars, $dumpoff, $dumpon, $fdisplay, $fmonitor, $fstrobe,
$fwrite, $history, $key, $list, $log, $monitor, $monitoroff, $monitoron, $nokey, $nolog, $printtimescale, $showscopes,
$showvariables, $showvars, $strobe, $timeformat, $write
</p><p>
</p></li></ol></div><p>
</p></div><div class="sect2" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="section.boundaries.analyzed.2001"></a>Verilog-2001 constructs</h3></div></div></div><p>
</p><div class="orderedlist"><ol type="1"><li><p>`ifndef and `elsif directives</p></li><li><p>`file and `line directives</p></li><li><p>Constant functions calls</p></li><li><p>Inline parameter passing by name</p></li><li><p>Localparam support</p></li><li><p>Implicit event sensitivity lists: <code class="code">@*</code></p></li><li><p>Comma-separated event lists (alternative to the "<code class="code">or</code>" keyword)</p></li><li><p>Signed value support</p></li><li><p>Immediate register assignment (i.e., <code class="code">reg a = 1'b0</code>)</p></li><li><p>Variable multi-bit selects (i.e., <code class="code">a[b+:3]</code>, <code class="code">a[b-:3]</code>)</p></li><li><p>Exponential power operator: <code class="code">a**b</code></p></li><li><p>Arithmetic shift operators: <code class="code"><<<, >>></code></p></li><li><p>Pre-port parameter listing (i.e., <code class="code">module foo #(parameter a=0) (...);</code>)</p></li><li><p>Inline port listing (i.e., <code class="code">module foo (input wire a, output reg b);</code>)</p></li><li><p>Attributes (note: Covered only performs attributes that it recognizes)</p></li><li><p>Arrays of instances</p></li><li><p>Generate blocks</p></li><li><p>"Automatic" or reentrant tasks/recursive functions</p></li><li><p>$value$plusargs system function call</p></li><li><p>
The following system tasks are allowed within logic blocks being considered for coverage:
</p><p>
$dumpports, $dumpportsall, $dumpportsoff, $dumpportson, $dumpportslimit, $dumpportsflush, $fclose, $ferror, $fflush,
$swrite, $swriteb, $swriteh, $swriteo, $ungetc
</p><p>
</p></li></ol></div><p>
</p></div><div class="sect2" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="section.boundaries.analyzed.sv"></a>SystemVerilog constructs</h3></div></div></div><div class="orderedlist"><ol type="1"><li><p>New integer types: <code class="code">char, byte, bit, logic, int, shortint, longint</code></p></li><li><p>Op-and-assign statements: <code class="code">+=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, >>>=, ++, --</code></p></li><li><p>Proper support for <code class="code">always_comb, always_latch, always_ff, final</code> blocks</p></li><li><p><code class="code">do..while</code> loops</p></li><li><p>Enumerations</p></li><li><p>Typedefs</p></li><li><p>$root scope support</p></li><li><p>Unnamed scope support</p></li><li><p>Multi-dimensional arrays including packed/unpacked dimensions and bit-select, part-select and slicing</p></li><li><p>Parsing support for <code class="code">unique</code> and <code class="code">priority</code> if/case labels</p></li><li><p>Parsing support for implicit .name ports (i.e., <code class="code">foo f( .a, .b, .c );</code>)</p></li><li><p>Parsing support for implicit .* ports (i.e., <code class="code">foo f( .* );</code>)</p></li><li><p>Parsing support for assertions, properties and sequences</p></li><li><p>Functional support for $urandom, $urandom_range, $srandom, $shortrealtobits, $bitstoshortreal</p></li></ol></div></div></div><div class="sect1" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="section.boundaries.unanalyzed"></a>3.2. What logic cannot be currently analyzed?</h2></div></div></div><div class="sect2" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="section.boundaries.unanalyzed.1995"></a>Verilog-1995 constructs</h3></div></div></div><p>
</p><div class="orderedlist"><ol type="1"><li><p>All gate types (i.e., <code class="code">buf, not, or, and,</code> etc.)</p></li><li><p>All user defined primitives (UDPs)</p></li><li><p>System task calls (or any $... call) that are not mentioned in the supported list above</p></li></ol></div><p>
</p></div><div class="sect2" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="section.boundaries.unanalyzed.2001"></a>Verilog-2001 constructs</h3></div></div></div><p>
</p><div class="orderedlist"><ol type="1"><li><p>Configuration statements</p></li></ol></div><p>
</p></div></div><div class="sect1" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="section.boundaries.handling"></a>3.3. What is done with code blocks that contain code that cannot be analyzed?</h2></div></div></div><p>
When logic is encountered that cannot be analyzed within an always, initial, task, function or named block, Covered will
disregard the entire always block. If the entire block cannot be analyzed, it does not try to get coverage statistics as
these will most likely be incorrect (i.e., disregarded logic could affect the state of the logic that is being covered).
</p></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="chapter.metrics.html"><img src="img/prev.gif" alt="Prev"></a> </td><td width="20%" align="center"><a accesskey="u" href="part.overview.html"><img src="img/up.gif" alt="Up"></a></td><td width="40%" align="right"> <a accesskey="n" href="chapter.race.html"><img src="img/next.gif" alt="Next"></a></td></tr><tr><td width="40%" align="left" valign="top">Chapter 2. Coverage Metrics </td><td width="20%" align="center"><a accesskey="h" href="index.html"><img src="img/home.gif" alt="Home"></a></td><td width="40%" align="right" valign="top"> Chapter 4. Race Condition Checking</td></tr></table></div></body></html>
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