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<a name="1"> 1</a> `define ST_STOP 3'b001
<a name="2"> 2</a> `define ST_GO 3'b010
<a name="3"> 3</a> `define ST_SLOW 3'b100
<a name="4"> 4</a>
<a name="5"> 5</a> module main;
<a name="6"> 6</a>
<a name="7"> 7</a> reg clk;
<a name="8"> 8</a> reg go;
<a name="9"> 9</a> wire [2:0] state;
<a name="10"> 10</a> reg [3:0] err_mem[0:15];
<a name="11"> 11</a> reg [4:0] err_cnt;
<a name="12"> 12</a>
<a name="13"> 13</a> fsma fsm1( clk, go, state );
<a name="14"> 14</a> fsmb fsm2( clk, go );
<a name="15"> 15</a>
<a name="16"> 16</a> initial begin
<a name="17"> 17</a> err_cnt = 0;
<a name="18"> 18</a> forever @(posedge clk)
<a name="19"> 19</a> begin
<a name="20"> 20</a> err_mem[err_cnt] = {(state[0] & state[1]), (state[0] & state[2]), (state[1] & state[2]), (state == 3'b000)};
<a name="21"> 21</a> if( !err_cnt[4] && (err_mem[err_cnt] != 0) )
<a name="22"> 22</a> err_cnt = err_cnt + 1;
<a name="23"> 23</a> end
<a name="24"> 24</a> end
<a name="25"> 25</a>
<a name="26"> 26</a> initial begin
<a name="27"> 27</a> $dumpfile( "example.vcd" );
<a name="28"> 28</a> $dumpvars( 0, main );
<a name="29"> 29</a> go = 1'b0;
<a name="30"> 30</a> repeat( 10 ) @(posedge clk);
<a name="31"> 31</a> go = 1'b1;
<a name="32"> 32</a> #10;
<a name="33"> 33</a> $finish;
<a name="34"> 34</a> end
<a name="35"> 35</a>
<a name="36"> 36</a> initial begin
<a name="37"> 37</a> clk = 1'b0;
<a name="38"> 38</a> forever #(1) clk = ~clk;
<a name="39"> 39</a> end
<a name="40"> 40</a>
<a name="41"> 41</a> endmodule
<a name="42"> 42</a>
<a name="43"> 43</a> module fsma( clk, go, state );
<a name="44"> 44</a>
<a name="45"> 45</a> input clk;
<a name="46"> 46</a> input go;
<a name="47"> 47</a> output [2:0] state;
<a name="48"> 48</a>
<a name="49"> 49</a> reg [2:0] next_state;
<a name="50"> 50</a> reg [2:0] state;
<a name="51"> 51</a>
<a name="52"> 52</a> initial begin
<a name="53"> 53</a> state = `ST_SLOW;
<a name="54"> 54</a> end
<a name="55"> 55</a>
<a name="56"> 56</a> always @(posedge clk) state <= next_state;
<a name="57"> 57</a>
<a name="58"> 58</a> (* covered_fsm, lights, is="state", os="next_state" *)
<a name="59"> 59</a> always @(state or go)
<a name="60"> 60</a> case( state )
<a name="61"> 61</a> `ST_STOP : next_state = go ? `ST_GO : `ST_STOP;
<a name="62"> 62</a> `ST_GO : next_state = go ? `ST_GO : `ST_SLOW;
<a name="63"> 63</a> `ST_SLOW : next_state = `ST_STOP;
<a name="64"> 64</a> endcase
<a name="65"> 65</a>
<a name="66"> 66</a> assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state );
<a name="67"> 67</a>
<a name="68"> 68</a> endmodule
<a name="69"> 69</a>
<a name="70"> 70</a> module fsmb( clk, go );
<a name="71"> 71</a>
<a name="72"> 72</a> input clk;
<a name="73"> 73</a> input go;
<a name="74"> 74</a>
<a name="75"> 75</a> reg [2:0] next_state;
<a name="76"> 76</a> reg [2:0] state;
<a name="77"> 77</a>
<a name="78"> 78</a> initial begin
<a name="79"> 79</a> state = `ST_STOP;
<a name="80"> 80</a> end
<a name="81"> 81</a>
<a name="82"> 82</a> always @(posedge clk) state <= next_state;
<a name="83"> 83</a>
<a name="84"> 84</a> (* covered_fsm, lights, is="state", os="next_state",
<a name="85"> 85</a> trans="3'b001->3'b010",
<a name="86"> 86</a> trans="3'b010->3'b100",
<a name="87"> 87</a> trans="3'b100->3'b001" *)
<a name="88"> 88</a> always @(state or go)
<a name="89"> 89</a> case( state )
<a name="90"> 90</a> `ST_STOP : next_state = go ? `ST_GO : `ST_STOP;
<a name="91"> 91</a> `ST_GO : next_state = go ? `ST_GO : `ST_SLOW;
<a name="92"> 92</a> `ST_SLOW : next_state = `ST_STOP;
<a name="93"> 93</a> endcase
<a name="94"> 94</a>
<a name="95"> 95</a> assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state );
<a name="96"> 96</a>
<a name="97"> 97</a> endmodule
</code></pre></body></html>
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