/usr/share/gEDA/sym/verilog/and5-1.sym is in geda-symbols 1:1.8.2-4.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 | v 20031231 1
L 300 800 700 800 3 0 0 0 -1 -1
L 300 200 700 200 3 0 0 0 -1 -1
L 300 200 300 800 3 0 0 0 -1 -1
A 700 500 300 270 180 3 0 0 0 -1 -1
L 300 800 300 1000 3 0 0 0 -1 -1
L 300 200 300 0 3 0 0 0 -1 -1
P 1000 500 1300 500 1 0 1
{
T 1000 500 5 8 0 0 0 0 1
pinnumber=OUT
T 1000 500 5 8 0 0 0 0 1
pinseq=1
}
P 300 100 0 100 1 0 1
{
T 300 100 5 8 0 0 0 0 1
pinnumber=IN0
T 300 100 5 8 0 0 0 0 1
pinseq=2
}
P 300 300 0 300 1 0 1
{
T 300 300 5 8 0 0 0 0 1
pinnumber=IN1
T 300 300 5 8 0 0 0 0 1
pinseq=3
}
P 300 500 0 500 1 0 1
{
T 300 500 5 8 0 0 0 0 1
pinnumber=IN2
T 300 500 5 8 0 0 0 0 1
pinseq=4
}
P 300 700 0 700 1 0 1
{
T 300 700 5 8 0 0 0 0 1
pinnumber=IN3
T 300 700 5 8 0 0 0 0 1
pinseq=5
}
P 300 900 0 900 1 0 1
{
T 300 900 5 8 0 0 0 0 1
pinnumber=IN4
T 300 900 5 8 0 0 0 0 1
pinseq=6
}
T 400 100 5 10 1 1 0 2 1
refdes=U?
T 400 100 5 8 0 0 0 0 1
device=and
T 400 200 5 8 0 0 0 0 1
VERILOG_PORTS=POSITIONAL
|