/usr/src/kernel-patches/diffs/rtai/hal-linux-2.4.36-i386-1.3-04.patch is in rtai-source 3.9.1-4.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
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--- 2.4.35.5/arch/i386/config.in 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/config.in 2007-12-22 16:46:39.000000000 +0100
@@ -272,6 +272,7 @@ endmenu
mainmenu_option next_comment
comment 'General setup'
+bool 'Interrupt pipeline' CONFIG_IPIPE
bool 'Networking support' CONFIG_NET
# Visual Workstation support is utterly broken.
diff -uNrp 2.4.35.5/arch/i386/defconfig 2.4.35.5-i386-ipipe/arch/i386/defconfig
--- 2.4.35.5/arch/i386/defconfig 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/defconfig 2007-12-22 16:46:39.000000000 +0100
@@ -948,3 +948,9 @@ CONFIG_LOG_BUF_SHIFT=0
CONFIG_CRC32=y
# CONFIG_ZLIB_INFLATE is not set
# CONFIG_ZLIB_DEFLATE is not set
+
+#
+# Interrupt pipeline
+#
+CONFIG_IPIPE=y
+# CONFIG_IPIPE_STATS is not set
diff -uNrp 2.4.35.5/arch/i386/kernel/Makefile 2.4.35.5-i386-ipipe/arch/i386/kernel/Makefile
--- 2.4.35.5/arch/i386/kernel/Makefile 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/Makefile 2007-12-22 16:46:39.000000000 +0100
@@ -14,7 +14,8 @@ all: kernel.o head.o init_task.o
O_TARGET := kernel.o
-export-objs := mca.o mtrr.o msr.o cpuid.o microcode.o i386_ksyms.o time.o setup.o
+export-objs := mca.o mtrr.o msr.o cpuid.o microcode.o i386_ksyms.o time.o setup.o \
+ ipipe-root.o ipipe-core.o
obj-y := process.o semaphore.o signal.o entry.o traps.o irq.o vm86.o \
ptrace.o i8259.o ioport.o ldt.o setup.o time.o sys_i386.o \
@@ -39,6 +40,7 @@ obj-$(CONFIG_APM) += apm.o
obj-$(CONFIG_ACPI_BOOT) += acpi.o earlyquirk.o
obj-$(CONFIG_ACPI_SLEEP) += acpi_wakeup.o
obj-$(CONFIG_SMP) += smp.o smpboot.o trampoline.o
+obj-$(CONFIG_IPIPE) += ipipe-root.o ipipe-core.o
obj-$(CONFIG_X86_LOCAL_APIC) += mpparse.o apic.o nmi.o
obj-$(CONFIG_X86_IO_APIC) += io_apic.o
obj-$(CONFIG_X86_VISWS_APIC) += visws_apic.o
diff -uNrp 2.4.35.5/arch/i386/kernel/apic.c 2.4.35.5-i386-ipipe/arch/i386/kernel/apic.c
--- 2.4.35.5/arch/i386/kernel/apic.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/apic.c 2007-12-22 16:46:39.000000000 +0100
@@ -1111,6 +1111,9 @@ unsigned int apic_timer_irqs [NR_CPUS];
void smp_apic_timer_interrupt(struct pt_regs * regs)
{
int cpu = smp_processor_id();
+#ifdef CONFIG_IPIPE
+ regs = __ipipe_tick_regs + cpu;
+#endif /* CONFIG_IPIPE */
/*
* the NMI deadlock-detector uses this.
@@ -1149,7 +1152,7 @@ asmlinkage void smp_spurious_interrupt(v
*/
v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
- ack_APIC_irq();
+ __ack_APIC_irq();
/* see sw-dev-man vol 3, chapter 7.4.13.5 */
printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
diff -uNrp 2.4.35.5/arch/i386/kernel/entry.S 2.4.35.5-i386-ipipe/arch/i386/kernel/entry.S
--- 2.4.35.5/arch/i386/kernel/entry.S 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/entry.S 2007-12-22 16:46:39.000000000 +0100
@@ -45,7 +45,45 @@
#include <linux/linkage.h>
#include <asm/segment.h>
#include <asm/smp.h>
+#include <asm/ipipe.h>
+#ifdef CONFIG_IPIPE
+#define CLI call SYMBOL_NAME(__ipipe_stall_root) ; sti
+#define STI call SYMBOL_NAME(__ipipe_unstall_root)
+#define STI_COND_HW sti
+#define EMULATE_ROOT_IRET(bypass) call SYMBOL_NAME(__ipipe_unstall_iret_root) ; \
+ ENTRY(bypass)
+#define CATCH_ROOT_SYSCALL(bypass1,bypass2) \
+ call SYMBOL_NAME(__ipipe_syscall_root) ; \
+ testl %eax,%eax ; \
+ js bypass1 ; \
+ jne bypass2 ; \
+ movl ORIG_EAX(%esp),%eax
+#define PUSH_XCODE(v) pushl $ SYMBOL_NAME( ex_/**/v )
+#define HANDLE_EXCEPTION(code) pushl %code ; /* WARNING: arg marshalling != 2.6 version */ \
+ call SYMBOL_NAME(__ipipe_handle_exception) ; \
+ addl $12,%esp ; \
+ testl %eax,%eax ; \
+ jnz restore_raw
+#define DIVERT_EXCEPTION(code) movl %esp, %eax ; \
+ movl $ SYMBOL_NAME ( ex_/**/code ) ,%edx ; \
+ call SYMBOL_NAME(__ipipe_divert_exception) ; \
+ testl %eax,%eax ; \
+ jnz restore_raw
+
+#else /* !CONFIG_IPIPE */
+#define CLI cli
+#define STI sti
+#define STI_COND_HW
+#define EMULATE_ROOT_IRET(bypass)
+#define CATCH_ROOT_SYSCALL(bypass1,bypass2)
+
+#define PUSH_XCODE(v) pushl $ SYMBOL_NAME(v)
+#define HANDLE_EXCEPTION(code) call *%code ; \
+ addl $8,%esp
+#define DIVERT_EXCEPTION(code)
+#endif /* CONFIG_IPIPE */
+
EBX = 0x00
ECX = 0x04
EDX = 0x08
@@ -184,6 +222,7 @@ ENTRY(lcall27)
ENTRY(ret_from_fork)
+ STI_COND_HW
pushl %ebx
call SYMBOL_NAME(schedule_tail)
addl $4, %esp
@@ -203,6 +242,9 @@ ENTRY(system_call)
pushl %eax # save orig_eax
SAVE_ALL
GET_CURRENT(%ebx)
+ /* %ebx is caller-saved, so that's ok to go through
+ __ipipe_syscall_root() without saving it. */
+ CATCH_ROOT_SYSCALL(ret_from_sys_call,restore_raw)
testb $0x02,tsk_ptrace(%ebx) # PT_TRACESYS
jne tracesys
cmpl $(NR_syscalls),%eax
@@ -210,17 +252,18 @@ ENTRY(system_call)
call *SYMBOL_NAME(sys_call_table)(,%eax,4)
movl %eax,EAX(%esp) # save the return value
ENTRY(ret_from_sys_call)
- cli # need_resched and signals atomic test
+ CLI # need_resched and signals atomic test
cmpl $0,need_resched(%ebx)
jne reschedule
cmpl $0,sigpending(%ebx)
jne signal_return
restore_all:
+ EMULATE_ROOT_IRET(restore_raw)
RESTORE_ALL
ALIGN
signal_return:
- sti # we can get here from an interrupt handler
+ STI # we can get here from an interrupt handler
testl $(VM_MASK),EFLAGS(%esp)
movl %esp,%eax
jne v86_signal_return
@@ -269,7 +312,7 @@ reschedule:
ENTRY(divide_error)
pushl $0 # no error code
- pushl $ SYMBOL_NAME(do_divide_error)
+ PUSH_XCODE(do_divide_error)
ALIGN
error_code:
pushl %ds
@@ -295,23 +338,23 @@ error_code:
movl %edx,%ds
movl %edx,%es
GET_CURRENT(%ebx)
- call *%edi
- addl $8,%esp
+ HANDLE_EXCEPTION(edi)
jmp ret_from_exception
ENTRY(coprocessor_error)
pushl $0
- pushl $ SYMBOL_NAME(do_coprocessor_error)
+ PUSH_XCODE(do_coprocessor_error)
jmp error_code
ENTRY(simd_coprocessor_error)
pushl $0
- pushl $ SYMBOL_NAME(do_simd_coprocessor_error)
+ PUSH_XCODE(do_simd_coprocessor_error)
jmp error_code
ENTRY(device_not_available)
pushl $-1 # mark this as an int
SAVE_ALL
+ DIVERT_EXCEPTION(device_not_available)
GET_CURRENT(%ebx)
movl %cr0,%eax
testl $0x4,%eax # EM (math emulation bit)
@@ -326,7 +369,7 @@ device_not_available_emulate:
ENTRY(debug)
pushl $0
- pushl $ SYMBOL_NAME(do_debug)
+ PUSH_XCODE(do_debug)
jmp error_code
ENTRY(nmi)
@@ -341,27 +384,27 @@ ENTRY(nmi)
ENTRY(int3)
pushl $0
- pushl $ SYMBOL_NAME(do_int3)
+ PUSH_XCODE(do_int3)
jmp error_code
ENTRY(overflow)
pushl $0
- pushl $ SYMBOL_NAME(do_overflow)
+ PUSH_XCODE(do_overflow)
jmp error_code
ENTRY(bounds)
pushl $0
- pushl $ SYMBOL_NAME(do_bounds)
+ PUSH_XCODE(do_bounds)
jmp error_code
ENTRY(invalid_op)
pushl $0
- pushl $ SYMBOL_NAME(do_invalid_op)
+ PUSH_XCODE(do_invalid_op)
jmp error_code
ENTRY(coprocessor_segment_overrun)
pushl $0
- pushl $ SYMBOL_NAME(do_coprocessor_segment_overrun)
+ PUSH_XCODE(do_coprocessor_segment_overrun)
jmp error_code
ENTRY(double_fault)
@@ -369,37 +412,37 @@ ENTRY(double_fault)
jmp error_code
ENTRY(invalid_TSS)
- pushl $ SYMBOL_NAME(do_invalid_TSS)
+ PUSH_XCODE(do_invalid_TSS)
jmp error_code
ENTRY(segment_not_present)
- pushl $ SYMBOL_NAME(do_segment_not_present)
+ PUSH_XCODE(do_segment_not_present)
jmp error_code
ENTRY(stack_segment)
- pushl $ SYMBOL_NAME(do_stack_segment)
+ PUSH_XCODE(do_stack_segment)
jmp error_code
ENTRY(general_protection)
- pushl $ SYMBOL_NAME(do_general_protection)
+ PUSH_XCODE(do_general_protection)
jmp error_code
ENTRY(alignment_check)
- pushl $ SYMBOL_NAME(do_alignment_check)
+ PUSH_XCODE(do_alignment_check)
jmp error_code
ENTRY(page_fault)
- pushl $ SYMBOL_NAME(do_page_fault)
+ PUSH_XCODE(do_page_fault)
jmp error_code
ENTRY(machine_check)
pushl $0
- pushl $ SYMBOL_NAME(do_machine_check)
+ PUSH_XCODE(do_machine_check)
jmp error_code
ENTRY(spurious_interrupt_bug)
pushl $0
- pushl $ SYMBOL_NAME(do_spurious_interrupt_bug)
+ PUSH_XCODE(do_spurious_interrupt_bug)
jmp error_code
.data
diff -uNrp 2.4.35.5/arch/i386/kernel/i8259.c 2.4.35.5-i386-ipipe/arch/i386/kernel/i8259.c
--- 2.4.35.5/arch/i386/kernel/i8259.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/i8259.c 2007-12-22 16:46:39.000000000 +0100
@@ -53,7 +53,7 @@ BUILD_COMMON_IRQ()
*/
BUILD_16_IRQS(0x0)
-#ifdef CONFIG_X86_IO_APIC
+#if defined(CONFIG_X86_IO_APIC) || (defined(CONFIG_IPIPE) && defined(CONFIG_X86_LOCAL_APIC))
/*
* The IO-APIC gives us many more interrupt sources. Most of these
* are unused but an SMP system is supposed to have enough memory ...
@@ -107,10 +107,10 @@ BUILD_SMP_INTERRUPT(spurious_interrupt,S
IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
-void (*interrupt[NR_IRQS])(void) = {
+void (*interrupt[NR_XIRQS])(void) = {
IRQLIST_16(0x0),
-#ifdef CONFIG_X86_IO_APIC
+#if defined(CONFIG_X86_IO_APIC) || (defined(CONFIG_IPIPE) && defined(CONFIG_X86_LOCAL_APIC))
IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
@@ -188,13 +188,13 @@ void disable_8259A_irq(unsigned int irq)
unsigned int mask = 1 << irq;
unsigned long flags;
- spin_lock_irqsave(&i8259A_lock, flags);
+ spin_lock_irqsave_hw(&i8259A_lock, flags);
cached_irq_mask |= mask;
if (irq & 8)
outb(cached_A1,0xA1);
else
outb(cached_21,0x21);
- spin_unlock_irqrestore(&i8259A_lock, flags);
+ spin_unlock_irqrestore_hw(&i8259A_lock, flags);
}
void enable_8259A_irq(unsigned int irq)
@@ -202,13 +202,14 @@ void enable_8259A_irq(unsigned int irq)
unsigned int mask = ~(1 << irq);
unsigned long flags;
- spin_lock_irqsave(&i8259A_lock, flags);
+ spin_lock_irqsave_hw(&i8259A_lock, flags);
cached_irq_mask &= mask;
if (irq & 8)
outb(cached_A1,0xA1);
else
outb(cached_21,0x21);
- spin_unlock_irqrestore(&i8259A_lock, flags);
+ ipipe_irq_unlock(irq);
+ spin_unlock_irqrestore_hw(&i8259A_lock, flags);
}
int i8259A_irq_pending(unsigned int irq)
@@ -217,12 +218,12 @@ int i8259A_irq_pending(unsigned int irq)
unsigned long flags;
int ret;
- spin_lock_irqsave(&i8259A_lock, flags);
+ spin_lock_irqsave_hw(&i8259A_lock, flags);
if (irq < 8)
ret = inb(0x20) & mask;
else
ret = inb(0xA0) & (mask >> 8);
- spin_unlock_irqrestore(&i8259A_lock, flags);
+ spin_unlock_irqrestore_hw(&i8259A_lock, flags);
return ret;
}
@@ -269,7 +270,7 @@ void mask_and_ack_8259A(unsigned int irq
unsigned int irqmask = 1 << irq;
unsigned long flags;
- spin_lock_irqsave(&i8259A_lock, flags);
+ spin_lock_irqsave_hw(&i8259A_lock, flags);
/*
* Lightweight spurious IRQ detection. We do not want
* to overdo spurious IRQ handling - it's usually a sign
@@ -287,6 +288,15 @@ void mask_and_ack_8259A(unsigned int irq
*/
if (cached_irq_mask & irqmask)
goto spurious_8259A_irq;
+#ifdef CONFIG_IPIPE
+ if (irq == 0) {
+ /* Fast timer ack -- don't mask (unless supposedly
+ spurious) */
+ outb(0x20,0x20);
+ spin_unlock_irqrestore_hw(&i8259A_lock, flags);
+ return;
+ }
+#endif /* CONFIG_IPIPE */
cached_irq_mask |= irqmask;
handle_real_irq:
@@ -300,7 +310,7 @@ handle_real_irq:
outb(cached_21,0x21);
outb(0x60+irq,0x20); /* 'Specific EOI' to master */
}
- spin_unlock_irqrestore(&i8259A_lock, flags);
+ spin_unlock_irqrestore_hw(&i8259A_lock, flags);
return;
spurious_8259A_irq:
@@ -338,7 +348,7 @@ void __init init_8259A(int auto_eoi)
{
unsigned long flags;
- spin_lock_irqsave(&i8259A_lock, flags);
+ spin_lock_irqsave_hw(&i8259A_lock, flags);
outb(0xff, 0x21); /* mask all of 8259A-1 */
outb(0xff, 0xA1); /* mask all of 8259A-2 */
@@ -374,7 +384,7 @@ void __init init_8259A(int auto_eoi)
outb(cached_21, 0x21); /* restore master IRQ mask */
outb(cached_A1, 0xA1); /* restore slave IRQ mask */
- spin_unlock_irqrestore(&i8259A_lock, flags);
+ spin_unlock_irqrestore_hw(&i8259A_lock, flags);
}
/*
@@ -455,7 +465,7 @@ void __init init_IRQ(void)
* us. (some of these will be overridden and become
* 'special' SMP interrupts)
*/
- for (i = 0; i < NR_IRQS; i++) {
+ for (i = 0; i < NR_XIRQS; i++) {
int vector = FIRST_EXTERNAL_VECTOR + i;
if (vector != SYSCALL_VECTOR)
set_intr_gate(vector, interrupt[i]);
diff -uNrp 2.4.35.5/arch/i386/kernel/io_apic.c 2.4.35.5-i386-ipipe/arch/i386/kernel/io_apic.c
--- 2.4.35.5/arch/i386/kernel/io_apic.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/io_apic.c 2007-12-22 16:46:39.000000000 +0100
@@ -151,18 +151,20 @@ static void mask_IO_APIC_irq (unsigned i
{
unsigned long flags;
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
+ ipipe_irq_lock(irq);
__mask_IO_APIC_irq(irq);
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
}
static void unmask_IO_APIC_irq (unsigned int irq)
{
unsigned long flags;
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
+ ipipe_irq_unlock(irq);
__unmask_IO_APIC_irq(irq);
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
}
void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
@@ -171,10 +173,10 @@ void clear_IO_APIC_pin(unsigned int apic
unsigned long flags;
/* Check delivery_mode to be sure we're not clearing an SMI pin */
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
*(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
*(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
if (entry.delivery_mode == dest_SMI)
return;
@@ -183,10 +185,10 @@ void clear_IO_APIC_pin(unsigned int apic
*/
memset(&entry, 0, sizeof(entry));
entry.mask = 1;
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
}
static void clear_IO_APIC (void)
@@ -691,10 +693,10 @@ void __init setup_IO_APIC_irqs(void)
if (!apic && (irq < 16))
disable_8259A_irq(irq);
}
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
}
}
@@ -739,10 +741,10 @@ void __init setup_ExtINT_IRQ0_pin(unsign
/*
* Add it to the IO-APIC irq-routing table:
*/
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
enable_8259A_irq(0);
}
@@ -1007,7 +1009,7 @@ void /*__init*/ print_PIC(void)
printk(KERN_DEBUG "\nprinting PIC contents\n");
- spin_lock_irqsave(&i8259A_lock, flags);
+ spin_lock_irqsave_hw(&i8259A_lock, flags);
v = inb(0xa1) << 8 | inb(0x21);
printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
@@ -1021,7 +1023,7 @@ void /*__init*/ print_PIC(void)
outb(0x0a,0xa0);
outb(0x0a,0x20);
- spin_unlock_irqrestore(&i8259A_lock, flags);
+ spin_unlock_irqrestore_hw(&i8259A_lock, flags);
printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
@@ -1231,14 +1233,15 @@ static unsigned int startup_edge_ioapic_
int was_pending = 0;
unsigned long flags;
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
if (irq < 16) {
disable_8259A_irq(irq);
if (i8259A_irq_pending(irq))
was_pending = 1;
}
__unmask_IO_APIC_irq(irq);
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ ipipe_irq_unlock(irq);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
return was_pending;
}
@@ -1250,6 +1253,24 @@ static unsigned int startup_edge_ioapic_
* interrupt for real. This prevents IRQ storms from unhandled
* devices.
*/
+#if CONFIG_IPIPE
+
+static void ack_edge_ioapic_irq (unsigned int irq)
+
+{
+ if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
+ == (IRQ_PENDING | IRQ_DISABLED)) {
+ unsigned long flags;
+ spin_lock_irqsave_hw(&ioapic_lock,flags);
+ __mask_IO_APIC_irq(irq);
+ spin_unlock_irqrestore_hw(&ioapic_lock,flags);
+ }
+
+ __ack_APIC_irq();
+}
+
+#else /* !CONFIG_IPIPE */
+
static void ack_edge_ioapic_irq(unsigned int irq)
{
if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
@@ -1258,6 +1279,8 @@ static void ack_edge_ioapic_irq(unsigned
ack_APIC_irq();
}
+#endif /* CONFIG_IPIPE */
+
static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ }
@@ -1286,6 +1309,58 @@ static unsigned int startup_level_ioapic
#define enable_level_ioapic_irq unmask_IO_APIC_irq
#define disable_level_ioapic_irq mask_IO_APIC_irq
+#ifdef CONFIG_IPIPE
+
+/* Prevent low priority IRQs grabbed by high priority domains from
+ being delayed, waiting for a high priority interrupt handler
+ running in a low priority domain to complete. */
+
+static unsigned long bugous_edge_triggers;
+
+static void end_level_ioapic_irq (unsigned irq)
+
+{
+ unsigned long flags;
+
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
+
+ if (test_and_clear_bit(irq,&bugous_edge_triggers)) {
+ atomic_inc(&irq_mis_count);
+ __unmask_and_level_IO_APIC_irq(irq);
+ }
+ else
+ __unmask_IO_APIC_irq(irq);
+
+ ipipe_irq_unlock(irq);
+
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
+}
+
+static void mask_and_ack_level_ioapic_irq (unsigned irq)
+
+{
+ unsigned long flags, v;
+ int i;
+
+ i = IO_APIC_VECTOR(irq);
+ v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
+
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
+
+ if (!(v & (1 << (i & 0x1f)))) {
+ set_bit(irq,&bugous_edge_triggers);
+ __mask_and_edge_IO_APIC_irq(irq);
+ }
+ else
+ __mask_IO_APIC_irq(irq);
+
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
+
+ __ack_APIC_irq();
+}
+
+#else /* !CONFIG_IPIPE */
+
static void end_level_ioapic_irq (unsigned int irq)
{
unsigned long v;
@@ -1347,6 +1422,8 @@ static void end_level_ioapic_irq (unsign
static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ }
+#endif /* CONFIG_IPIPE */
+
#ifndef CONFIG_SMP
void fastcall send_IPI_self(int vector)
@@ -1381,9 +1458,9 @@ static void set_ioapic_affinity (unsigne
*/
mask = mask << 24;
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
__DO_ACTION(1, = mask, )
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
}
/*
@@ -1466,7 +1543,7 @@ static void disable_lapic_irq (unsigned
static void ack_lapic_irq (unsigned int irq)
{
- ack_APIC_irq();
+ __ack_APIC_irq();
}
static void end_lapic_irq (unsigned int i) { /* nothing */ }
@@ -1883,10 +1960,10 @@ int io_apic_set_pci_routing (int ioapic,
if (!ioapic && (irq < 16))
disable_8259A_irq(irq);
- spin_lock_irqsave(&ioapic_lock, flags);
+ spin_lock_irqsave_hw(&ioapic_lock, flags);
io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
- spin_unlock_irqrestore(&ioapic_lock, flags);
+ spin_unlock_irqrestore_hw(&ioapic_lock, flags);
return 0;
}
diff -uNrp 2.4.35.5/arch/i386/kernel/ipipe-core.c 2.4.35.5-i386-ipipe/arch/i386/kernel/ipipe-core.c
--- 2.4.35.5/arch/i386/kernel/ipipe-core.c 1970-01-01 01:00:00.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/ipipe-core.c 2007-12-22 16:46:39.000000000 +0100
@@ -0,0 +1,253 @@
+/* -*- linux-c -*-
+ * linux/arch/i386/kernel/ipipe-core.c
+ *
+ * Copyright (C) 2002-2005 Philippe Gerum.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Architecture-dependent I-PIPE core support for x86.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/hw_irq.h>
+#include <asm/irq.h>
+#include <asm/desc.h>
+#include <asm/io.h>
+#ifdef CONFIG_X86_LOCAL_APIC
+#include <asm/fixmap.h>
+#include <asm/bitops.h>
+#include <asm/mpspec.h>
+#ifdef CONFIG_X86_IO_APIC
+#include <asm/io_apic.h>
+#endif /* CONFIG_X86_IO_APIC */
+#include <asm/apic.h>
+#endif /* CONFIG_X86_LOCAL_APIC */
+
+struct pt_regs __ipipe_tick_regs[IPIPE_NR_CPUS];
+
+int __ipipe_tick_irq;
+
+#ifdef CONFIG_SMP
+
+static cpumask_t __ipipe_cpu_sync_map;
+
+static cpumask_t __ipipe_cpu_lock_map;
+
+static ipipe_spinlock_t __ipipe_cpu_barrier = IPIPE_SPIN_LOCK_UNLOCKED;
+
+static atomic_t __ipipe_critical_count = ATOMIC_INIT(0);
+
+static void (*__ipipe_cpu_sync) (void);
+
+void __ipipe_send_IPI_allbutself(int vector);
+
+#endif /* CONFIG_SMP */
+
+int __ipipe_ack_system_irq(unsigned irq)
+{
+#ifdef CONFIG_X86_LOCAL_APIC
+ __ack_APIC_irq();
+#endif /* CONFIG_X86_LOCAL_APIC */
+ return 1;
+}
+
+#ifdef CONFIG_SMP
+
+/* Always called with hw interrupts off. */
+
+void __ipipe_do_critical_sync(unsigned irq, void *cookie)
+{
+ ipipe_declare_cpuid;
+
+ ipipe_load_cpuid();
+
+ cpu_set(cpuid, __ipipe_cpu_sync_map);
+
+ /* Now we are in sync with the lock requestor running on another
+ CPU. Enter a spinning wait until he releases the global
+ lock. */
+ spin_lock_hw(&__ipipe_cpu_barrier);
+
+ /* Got it. Now get out. */
+
+ if (__ipipe_cpu_sync)
+ /* Call the sync routine if any. */
+ __ipipe_cpu_sync();
+
+ spin_unlock_hw(&__ipipe_cpu_barrier);
+
+ cpu_clear(cpuid, __ipipe_cpu_sync_map);
+}
+
+#endif /* CONFIG_SMP */
+
+/* ipipe_critical_enter() -- Grab the superlock excluding all CPUs
+ but the current one from a critical section. This lock is used when
+ we must enforce a global critical section for a single CPU in a
+ possibly SMP system whichever context the CPUs are running. */
+
+unsigned long ipipe_critical_enter(void (*syncfn) (void))
+{
+ unsigned long flags;
+
+ local_irq_save_hw(flags);
+
+#ifdef CONFIG_SMP
+ if (num_online_cpus() > 1) { /* We might be running a SMP-kernel on a UP box... */
+ ipipe_declare_cpuid;
+ cpumask_t lock_map;
+
+ ipipe_load_cpuid();
+
+ if (!cpu_test_and_set(cpuid, __ipipe_cpu_lock_map)) {
+ while (cpu_test_and_set
+ (BITS_PER_LONG - 1, __ipipe_cpu_lock_map)) {
+ int n = 0;
+ do {
+ cpu_relax();
+ } while (++n < cpuid);
+ }
+
+ spin_lock_hw(&__ipipe_cpu_barrier);
+
+ __ipipe_cpu_sync = syncfn;
+
+ /* Send the sync IPI to all processors but the current one. */
+ __ipipe_send_IPI_allbutself(IPIPE_CRITICAL_VECTOR);
+
+ cpus_andnot(lock_map, cpu_online_map,
+ __ipipe_cpu_lock_map);
+
+ while (!cpus_equal(__ipipe_cpu_sync_map, lock_map))
+ cpu_relax();
+ }
+
+ atomic_inc(&__ipipe_critical_count);
+ }
+#endif /* CONFIG_SMP */
+
+ return flags;
+}
+
+/* ipipe_critical_exit() -- Release the superlock. */
+
+void ipipe_critical_exit(unsigned long flags)
+{
+#ifdef CONFIG_SMP
+ if (num_online_cpus() > 1) { /* We might be running a SMP-kernel on a UP box... */
+ ipipe_declare_cpuid;
+
+ ipipe_load_cpuid();
+
+ if (atomic_dec_and_test(&__ipipe_critical_count)) {
+ spin_unlock_hw(&__ipipe_cpu_barrier);
+
+ while (!cpus_empty(__ipipe_cpu_sync_map))
+ cpu_relax();
+
+ cpu_clear(cpuid, __ipipe_cpu_lock_map);
+ cpu_clear(BITS_PER_LONG - 1, __ipipe_cpu_lock_map);
+ }
+ }
+#endif /* CONFIG_SMP */
+
+ local_irq_restore_hw(flags);
+}
+
+/* ipipe_trigger_irq() -- Push the interrupt at front of the pipeline
+ just like if it has been actually received from a hw source. Also
+ works for virtual interrupts. */
+
+int fastcall ipipe_trigger_irq(unsigned irq)
+{
+ struct pt_regs regs;
+ unsigned long flags;
+
+ if (irq >= IPIPE_NR_IRQS ||
+ (ipipe_virtual_irq_p(irq) &&
+ !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
+ return -EINVAL;
+
+ local_irq_save_hw(flags);
+
+ regs.orig_eax = irq; /* Won't be acked */
+ regs.xcs = __KERNEL_CS;
+ regs.eflags = flags;
+
+ __ipipe_handle_irq(regs);
+
+ local_irq_restore_hw(flags);
+
+ return 1;
+}
+
+int ipipe_get_sysinfo(struct ipipe_sysinfo *info)
+{
+ info->ncpus = num_online_cpus();
+ info->cpufreq = ipipe_cpu_freq();
+ info->archdep.tmirq = __ipipe_tick_irq;
+#ifdef CONFIG_X86_TSC
+ info->archdep.tmfreq = ipipe_cpu_freq();
+#else /* !CONFIG_X86_TSC */
+ info->archdep.tmfreq = CLOCK_TICK_RATE;
+#endif /* CONFIG_X86_TSC */
+
+ return 0;
+}
+
+int ipipe_tune_timer (unsigned long ns, int flags)
+
+{
+ unsigned hz, latch;
+ unsigned long x;
+
+ if (flags & IPIPE_RESET_TIMER)
+ latch = LATCH;
+ else {
+ hz = 1000000000 / ns;
+
+ if (hz < HZ)
+ return -EINVAL;
+
+ latch = (CLOCK_TICK_RATE + hz/2) / hz;
+ }
+
+ x = ipipe_critical_enter(NULL); /* Sync with all CPUs */
+
+ /* Shamelessly lifted from init_IRQ() in i8259.c */
+ outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */
+ outb_p(latch & 0xff,0x40); /* LSB */
+ outb(latch >> 8,0x40); /* MSB */
+
+ ipipe_critical_exit(x);
+
+ return 0;
+}
+
+EXPORT_SYMBOL(__ipipe_tick_irq);
+EXPORT_SYMBOL(ipipe_critical_enter);
+EXPORT_SYMBOL(ipipe_critical_exit);
+EXPORT_SYMBOL(ipipe_trigger_irq);
+EXPORT_SYMBOL(ipipe_get_sysinfo);
+EXPORT_SYMBOL(ipipe_tune_timer);
diff -uNrp 2.4.35.5/arch/i386/kernel/ipipe-root.c 2.4.35.5-i386-ipipe/arch/i386/kernel/ipipe-root.c
--- 2.4.35.5/arch/i386/kernel/ipipe-root.c 1970-01-01 01:00:00.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/ipipe-root.c 2007-12-22 16:46:39.000000000 +0100
@@ -0,0 +1,576 @@
+/* -*- linux-c -*-
+ * linux/arch/i386/kernel/ipipe-root.c
+ *
+ * Copyright (C) 2002-2005 Philippe Gerum.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Architecture-dependent I-PIPE support for x86.
+ */
+
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/smp.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/vt_kern.h>
+#include <linux/sys.h>
+#include <asm/unistd.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
+#include <asm/hw_irq.h>
+#include <asm/irq.h>
+#include <asm/desc.h>
+#include <asm/io.h>
+#ifdef CONFIG_X86_LOCAL_APIC
+#include <asm/fixmap.h>
+#include <asm/bitops.h>
+#include <asm/mpspec.h>
+#ifdef CONFIG_X86_IO_APIC
+#include <asm/io_apic.h>
+#endif /* CONFIG_X86_IO_APIC */
+#include <asm/apic.h>
+
+static int __ipipe_noack_irq(unsigned irq)
+{
+ return 1;
+}
+#endif /* CONFIG_X86_LOCAL_APIC */
+
+asmlinkage unsigned int do_IRQ(struct pt_regs *regs);
+void smp_apic_timer_interrupt(struct pt_regs *regs);
+asmlinkage void smp_spurious_interrupt(struct pt_regs *regs);
+asmlinkage void smp_error_interrupt(struct pt_regs *regs);
+asmlinkage void smp_reschedule_interrupt(struct pt_regs *regs);
+asmlinkage void smp_invalidate_interrupt(struct pt_regs *regs);
+asmlinkage void smp_call_function_interrupt(struct pt_regs *regs);
+
+static int __ipipe_ack_common_irq(unsigned irq)
+{
+ irq_desc_t *desc = irq_desc + irq;
+ unsigned long flags;
+ ipipe_declare_cpuid;
+
+ ipipe_load_cpuid(); /* hw interrupts are off. */
+ flags = ipipe_test_and_stall_pipeline();
+ desc->handler->ack(irq);
+ ipipe_restore_pipeline_nosync(ipipe_percpu_domain[cpuid], flags, cpuid);
+
+ return 1;
+}
+
+#ifdef CONFIG_X86_LOCAL_APIC
+
+static void __ipipe_null_handler(unsigned irq, void *cookie)
+{
+ /* Nop. */
+}
+
+#ifdef CONFIG_SMP
+
+static int __ipipe_boot_cpuid(void)
+{
+ return 0;
+}
+
+u8 __ipipe_apicid_2_cpu[IPIPE_NR_CPUS];
+
+static int __ipipe_hard_cpuid(void)
+{
+ unsigned long flags;
+ int cpu;
+
+ local_irq_save_hw(flags);
+ cpu = __ipipe_apicid_2_cpu[GET_APIC_ID(apic_read(APIC_ID))];
+ local_irq_restore_hw(flags);
+ return cpu;
+}
+
+int (*__ipipe_logical_cpuid)(void) = &__ipipe_boot_cpuid;
+
+EXPORT_SYMBOL(__ipipe_logical_cpuid);
+
+#endif /* CONFIG_SMP */
+
+#endif /* CONFIG_X86_LOCAL_APIC */
+
+/* __ipipe_enable_pipeline() -- We are running on the boot CPU, hw
+ interrupts are off, and secondary CPUs are still lost in space. */
+
+void __init __ipipe_enable_pipeline(void)
+{
+ unsigned irq;
+
+#ifdef CONFIG_X86_LOCAL_APIC
+
+ /* Map the APIC system vectors. */
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ LOCAL_TIMER_VECTOR - FIRST_EXTERNAL_VECTOR,
+ (ipipe_irq_handler_t)&smp_apic_timer_interrupt,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ SPURIOUS_APIC_VECTOR - FIRST_EXTERNAL_VECTOR,
+ (ipipe_irq_handler_t)&smp_spurious_interrupt,
+ NULL,
+ &__ipipe_noack_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ ERROR_APIC_VECTOR - FIRST_EXTERNAL_VECTOR,
+ (ipipe_irq_handler_t)&smp_error_interrupt,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ IPIPE_SERVICE_VECTOR0 - FIRST_EXTERNAL_VECTOR,
+ &__ipipe_null_handler,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ IPIPE_SERVICE_VECTOR1 - FIRST_EXTERNAL_VECTOR,
+ &__ipipe_null_handler,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ IPIPE_SERVICE_VECTOR2 - FIRST_EXTERNAL_VECTOR,
+ &__ipipe_null_handler,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ IPIPE_SERVICE_VECTOR3 - FIRST_EXTERNAL_VECTOR,
+ &__ipipe_null_handler,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ __ipipe_tick_irq =
+ using_apic_timer ? LOCAL_TIMER_VECTOR - FIRST_EXTERNAL_VECTOR : 0;
+
+#else /* !CONFIG_X86_LOCAL_APIC */
+
+ __ipipe_tick_irq = 0;
+
+#endif /* CONFIG_X86_LOCAL_APIC */
+
+#ifdef CONFIG_SMP
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ RESCHEDULE_VECTOR - FIRST_EXTERNAL_VECTOR,
+ (ipipe_irq_handler_t)&smp_reschedule_interrupt,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ INVALIDATE_TLB_VECTOR - FIRST_EXTERNAL_VECTOR,
+ (ipipe_irq_handler_t)&smp_invalidate_interrupt,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ ipipe_virtualize_irq(ipipe_root_domain,
+ CALL_FUNCTION_VECTOR - FIRST_EXTERNAL_VECTOR,
+ (ipipe_irq_handler_t)&smp_call_function_interrupt,
+ NULL,
+ &__ipipe_ack_system_irq,
+ IPIPE_STDROOT_MASK);
+
+ /* Some guest O/S may run tasks over non-Linux stacks, so we
+ * cannot rely on the regular definition of smp_processor_id()
+ * on x86 to fetch the logical cpu id. We fix this by using
+ * our own private physical apicid -> logicial cpuid mapping
+ * as soon as the pipeline is enabled, so that
+ * ipipe_processor_id() always do the right thing, regardless
+ * of the current stack setup. Also note that the pipeline is
+ * enabled after the APIC space has been mapped in
+ * trap_init(), so it's safe to use it. */
+
+ __ipipe_logical_cpuid = &__ipipe_hard_cpuid;
+
+#endif /* CONFIG_SMP */
+
+ /* Finally, virtualize the remaining ISA and IO-APIC
+ * interrupts. Interrupts which have already been virtualized
+ * will just beget a silent -EPERM error since
+ * IPIPE_SYSTEM_MASK has been passed for them, that's ok. */
+
+ for (irq = 0; irq < NR_IRQS; irq++) {
+ /* Fails for IPIPE_CRITICAL_IPI but that's ok. */
+ ipipe_virtualize_irq(ipipe_root_domain,
+ irq,
+ (ipipe_irq_handler_t)&do_IRQ,
+ NULL,
+ &__ipipe_ack_common_irq,
+ IPIPE_STDROOT_MASK);
+ }
+
+#ifdef CONFIG_X86_LOCAL_APIC
+ /* Eventually allow these vectors to be reprogrammed. */
+ ipipe_root_domain->irqs[IPIPE_SERVICE_IPI0].control &= ~IPIPE_SYSTEM_MASK;
+ ipipe_root_domain->irqs[IPIPE_SERVICE_IPI1].control &= ~IPIPE_SYSTEM_MASK;
+ ipipe_root_domain->irqs[IPIPE_SERVICE_IPI2].control &= ~IPIPE_SYSTEM_MASK;
+ ipipe_root_domain->irqs[IPIPE_SERVICE_IPI3].control &= ~IPIPE_SYSTEM_MASK;
+#endif /* CONFIG_X86_LOCAL_APIC */
+}
+
+static inline void __fixup_if(struct pt_regs *regs)
+{
+ ipipe_declare_cpuid;
+ unsigned long flags;
+
+ ipipe_get_cpu(flags);
+
+ if (ipipe_percpu_domain[cpuid] == ipipe_root_domain) {
+ /* Have the saved hw state look like the domain stall bit, so
+ that __ipipe_unstall_iret_root() restores the proper
+ pipeline state for the root stage upon exit. */
+
+ if (test_bit
+ (IPIPE_STALL_FLAG,
+ &ipipe_root_domain->cpudata[cpuid].status))
+ regs->eflags &= ~X86_EFLAGS_IF;
+ else
+ regs->eflags |= X86_EFLAGS_IF;
+ }
+
+ ipipe_put_cpu(flags);
+}
+
+asmlinkage void __ipipe_unstall_iret_root(struct pt_regs regs)
+{
+ ipipe_declare_cpuid;
+
+ /* Emulate IRET's handling of the interrupt flag. */
+
+ local_irq_disable_hw();
+
+ ipipe_load_cpuid();
+
+ /* Restore the software state as it used to be on kernel
+ entry. CAUTION: NMIs must *not* return through this
+ emulation. */
+
+ if (!(regs.eflags & X86_EFLAGS_IF)) {
+ __set_bit(IPIPE_STALL_FLAG,
+ &ipipe_root_domain->cpudata[cpuid].status);
+ regs.eflags |= X86_EFLAGS_IF;
+ } else {
+ __clear_bit(IPIPE_STALL_FLAG,
+ &ipipe_root_domain->cpudata[cpuid].status);
+
+ /* Only sync virtual IRQs here, so that we don't recurse
+ indefinitely in case of an external interrupt flood. */
+
+ if ((ipipe_root_domain->cpudata[cpuid].
+ irq_pending_hi & IPIPE_IRQMASK_VIRT) != 0)
+ __ipipe_sync_pipeline(IPIPE_IRQMASK_VIRT);
+ }
+}
+
+asmlinkage int __ipipe_syscall_root(struct pt_regs regs)
+{
+ ipipe_declare_cpuid;
+ unsigned long flags;
+
+ __fixup_if(®s);
+
+ /* This routine either returns:
+ 0 -- if the syscall is to be passed to Linux;
+ >0 -- if the syscall should not be passed to Linux, and no
+ tail work should be performed;
+ <0 -- if the syscall should not be passed to Linux but the
+ tail work has to be performed (for handling signals etc). */
+
+ if (__ipipe_syscall_watched_p(current, regs.orig_eax) &&
+ __ipipe_event_monitored_p(IPIPE_EVENT_SYSCALL) &&
+ __ipipe_dispatch_event(IPIPE_EVENT_SYSCALL,®s) > 0) {
+ /* We might enter here over a non-root domain and exit
+ * over the root one as a result of the syscall
+ * (i.e. by recycling the register set of the current
+ * context across the migration), so we need to fixup
+ * the interrupt flag upon return too, so that
+ * __ipipe_unstall_iret_root() resets the correct
+ * stall bit on exit. */
+ __fixup_if(®s);
+
+ if (ipipe_current_domain == ipipe_root_domain) {
+ /* Sync pending VIRQs before _TIF_NEED_RESCHED
+ * is tested. */
+ ipipe_lock_cpu(flags);
+ if ((ipipe_root_domain->cpudata[cpuid].irq_pending_hi & IPIPE_IRQMASK_VIRT) != 0)
+ __ipipe_sync_stage(IPIPE_IRQMASK_VIRT);
+ ipipe_unlock_cpu(flags);
+ return -1;
+ }
+ return 1;
+ }
+
+ return 0;
+}
+
+asmlinkage void do_divide_error(struct pt_regs *regs, long error_code);
+asmlinkage void do_debug(struct pt_regs *regs, long error_code);
+asmlinkage void do_int3(struct pt_regs *regs, long error_code);
+asmlinkage void do_overflow(struct pt_regs *regs, long error_code);
+asmlinkage void do_bounds(struct pt_regs *regs, long error_code);
+asmlinkage void do_invalid_op(struct pt_regs *regs, long error_code);
+asmlinkage void do_coprocessor_segment_overrun(struct pt_regs *regs, long error_code);
+asmlinkage void do_double_fault(struct pt_regs *regs, long error_code);
+asmlinkage void do_invalid_TSS(struct pt_regs *regs, long error_code);
+asmlinkage void do_segment_not_present(struct pt_regs *regs, long error_code);
+asmlinkage void do_stack_segment(struct pt_regs *regs, long error_code);
+asmlinkage void do_general_protection(struct pt_regs *regs, long error_code);
+asmlinkage void do_page_fault(struct pt_regs *regs, long error_code);
+asmlinkage void do_spurious_interrupt_bug(struct pt_regs *regs, long error_code);
+asmlinkage void do_coprocessor_error(struct pt_regs *regs, long error_code);
+asmlinkage void do_alignment_check(struct pt_regs *regs, long error_code);
+asmlinkage void do_machine_check(struct pt_regs *regs, long error_code);
+asmlinkage void do_simd_coprocessor_error(struct pt_regs *regs, long error_code);
+
+/* Work around genksyms's issue with over-qualification in decls. */
+
+typedef asmlinkage void __ipipe_exhandler(struct pt_regs *, long);
+
+typedef __ipipe_exhandler *__ipipe_exptr;
+
+static __ipipe_exptr __ipipe_std_extable[] = {
+
+ [ex_do_divide_error] = &do_divide_error,
+ [ex_do_debug] = &do_debug,
+ [ex_do_int3] = &do_int3,
+ [ex_do_overflow] = &do_overflow,
+ [ex_do_bounds] = &do_bounds,
+ [ex_do_invalid_op] = &do_invalid_op,
+ [ex_do_coprocessor_segment_overrun] = &do_coprocessor_segment_overrun,
+ [ex_do_double_fault] = &do_double_fault,
+ [ex_do_invalid_TSS] = &do_invalid_TSS,
+ [ex_do_segment_not_present] = &do_segment_not_present,
+ [ex_do_stack_segment] = &do_stack_segment,
+ [ex_do_general_protection] = do_general_protection,
+ [ex_do_page_fault] = &do_page_fault,
+ [ex_do_spurious_interrupt_bug] = &do_spurious_interrupt_bug,
+ [ex_do_coprocessor_error] = &do_coprocessor_error,
+ [ex_do_alignment_check] = &do_alignment_check,
+ [ex_do_machine_check] = &do_machine_check,
+ [ex_do_simd_coprocessor_error] = &do_simd_coprocessor_error
+};
+
+asmlinkage int __ipipe_handle_exception(int vector, struct pt_regs *regs, long error_code)
+{
+ if (!__ipipe_event_monitored_p(vector) ||
+ __ipipe_dispatch_event(vector,regs) == 0) {
+ __ipipe_exptr handler = __ipipe_std_extable[vector];
+ handler(regs,error_code);
+ __fixup_if(regs);
+ return 0;
+ }
+
+ return 1;
+}
+
+int FASTCALL(__ipipe_divert_exception(struct pt_regs *regs, int vector));
+
+int fastcall __ipipe_divert_exception(struct pt_regs *regs, int vector)
+{
+ if (__ipipe_event_monitored_p(vector) &&
+ __ipipe_dispatch_event(vector,regs) != 0)
+ return 1;
+
+ __fixup_if(regs);
+
+ return 0;
+}
+
+/* __ipipe_handle_irq() -- IPIPE's generic IRQ handler. An optimistic
+ interrupt protection log is maintained here for each domain. Hw
+ interrupts are off on entry. */
+
+int __ipipe_handle_irq(struct pt_regs regs)
+{
+ struct ipipe_domain *this_domain, *next_domain;
+ unsigned irq = regs.orig_eax;
+ struct list_head *head, *pos;
+ ipipe_declare_cpuid;
+ int m_ack, s_ack;
+
+ ipipe_load_cpuid();
+
+ if (regs.orig_eax < 0) {
+ irq &= 0xff;
+ m_ack = 0;
+ } else
+ m_ack = 1;
+
+ this_domain = ipipe_percpu_domain[cpuid];
+
+ if (test_bit(IPIPE_STICKY_FLAG, &this_domain->irqs[irq].control))
+ head = &this_domain->p_link;
+ else {
+ head = __ipipe_pipeline.next;
+ next_domain = list_entry(head, struct ipipe_domain, p_link);
+ if (likely(test_bit(IPIPE_WIRED_FLAG, &next_domain->irqs[irq].control))) {
+ if (!m_ack && next_domain->irqs[irq].acknowledge != NULL)
+ next_domain->irqs[irq].acknowledge(irq);
+ if (likely(__ipipe_dispatch_wired(next_domain, irq)))
+ goto finalize;
+ else
+ goto finalize_nosync;
+ }
+ }
+
+ /* Ack the interrupt. */
+
+ s_ack = m_ack;
+ pos = head;
+
+ while (pos != &__ipipe_pipeline) {
+ next_domain = list_entry(pos, struct ipipe_domain, p_link);
+
+ /* For each domain handling the incoming IRQ, mark it as
+ pending in its log. */
+
+ if (test_bit
+ (IPIPE_HANDLE_FLAG, &next_domain->irqs[irq].control)) {
+ /* Domains that handle this IRQ are polled for
+ acknowledging it by decreasing priority order. The
+ interrupt must be made pending _first_ in the domain's
+ status flags before the PIC is unlocked. */
+
+ next_domain->cpudata[cpuid].irq_counters[irq].total_hits++;
+ next_domain->cpudata[cpuid].irq_counters[irq].pending_hits++;
+ __ipipe_set_irq_bit(next_domain, cpuid, irq);
+
+ /* Always get the first master acknowledge available. Once
+ we've got it, allow slave acknowledge handlers to run
+ (until one of them stops us). */
+
+ if (!m_ack)
+ m_ack = next_domain->irqs[irq].acknowledge(irq);
+ else if (test_bit
+ (IPIPE_SHARED_FLAG,
+ &next_domain->irqs[irq].control) && !s_ack)
+ s_ack = next_domain->irqs[irq].acknowledge(irq);
+ }
+
+ /* If the domain does not want the IRQ to be passed down the
+ interrupt pipe, exit the loop now. */
+
+ if (!test_bit(IPIPE_PASS_FLAG, &next_domain->irqs[irq].control))
+ break;
+
+ pos = next_domain->p_link.next;
+ }
+
+ if (irq == __ipipe_tick_irq &&
+ __ipipe_pipeline_head_p(ipipe_root_domain) &&
+ ipipe_root_domain->cpudata[cpuid].irq_counters[irq].pending_hits > 1)
+ /*
+ * Emulate a loss of clock ticks if Linux is owning
+ * the time source. The drift will be compensated by
+ * the timer support code.
+ */
+ ipipe_root_domain->cpudata[cpuid].irq_counters[irq].pending_hits = 1;
+
+finalize:
+
+ if (irq == __ipipe_tick_irq) {
+ __ipipe_tick_regs[cpuid].eflags = regs.eflags;
+ __ipipe_tick_regs[cpuid].eip = regs.eip;
+ __ipipe_tick_regs[cpuid].xcs = regs.xcs;
+#if defined(CONFIG_SMP) && defined(CONFIG_FRAME_POINTER)
+ /* Linux profiling code needs this. */
+ __ipipe_tick_regs[cpuid].ebp = regs.ebp;
+#endif /* CONFIG_SMP && CONFIG_FRAME_POINTER */
+ }
+
+ /* Now walk the pipeline, yielding control to the highest
+ priority domain that has pending interrupt(s) or
+ immediately to the current domain if the interrupt has been
+ marked as 'sticky'. This search does not go beyond the
+ current domain in the pipeline. */
+
+ __ipipe_walk_pipeline(head, cpuid);
+
+finalize_nosync:
+
+ ipipe_load_cpuid();
+
+ if (ipipe_percpu_domain[cpuid] != ipipe_root_domain ||
+ test_bit(IPIPE_STALL_FLAG,
+ &ipipe_root_domain->cpudata[cpuid].status))
+ return 0;
+
+#ifdef CONFIG_SMP
+ /* Prevent a spurious rescheduling from being triggered on
+ preemptible kernels along the way out through
+ ret_from_intr. */
+ if (regs.orig_eax < 0)
+ __set_bit(IPIPE_STALL_FLAG, &ipipe_root_domain->cpudata[cpuid].status);
+#endif /* CONFIG_SMP */
+
+ return 1;
+}
+
+void *ipipe_irq_handler = __ipipe_handle_irq;
+EXPORT_SYMBOL(ipipe_irq_handler);
+EXPORT_SYMBOL(io_apic_irqs);
+EXPORT_SYMBOL(__ipipe_tick_regs);
+extern void *do_signal;
+EXPORT_SYMBOL(do_signal);
+extern void ret_from_intr(void);
+EXPORT_SYMBOL(ret_from_intr);
+extern struct desc_struct idt_table[];
+EXPORT_SYMBOL(idt_table);
+extern spinlock_t i8259A_lock;
+EXPORT_SYMBOL(i8259A_lock);
+#ifdef CONFIG_VT
+extern void (*kd_mksound)(unsigned int hz, unsigned int ticks);
+EXPORT_SYMBOL_NOVERS(kd_mksound);
+#endif /* CONFIG_VT */
+
+extern unsigned long cpu_khz;
+EXPORT_SYMBOL_GPL(cpu_khz);
+#ifdef CONFIG_SMP
+extern struct tlb_state cpu_tlbstate[];
+EXPORT_SYMBOL_NOVERS(cpu_tlbstate);
+extern spinlock_t nmi_print_lock;
+EXPORT_SYMBOL_GPL(nmi_print_lock);
+#endif /* CONFIG_SMP */
+extern irq_desc_t irq_desc[];
+EXPORT_SYMBOL_NOVERS(irq_desc);
+EXPORT_SYMBOL_NOVERS(default_ldt);
+EXPORT_SYMBOL_NOVERS(__switch_to);
+extern void show_stack(unsigned long *);
+EXPORT_SYMBOL_NOVERS(show_stack);
+EXPORT_SYMBOL_GPL(init_tss);
+EXPORT_SYMBOL_GPL(set_ldt_desc);
+EXPORT_SYMBOL_GPL(do_exit);
+void (*nmi_watchdog_tick) (struct pt_regs * regs);
+EXPORT_SYMBOL_GPL(nmi_watchdog_tick);
+
diff -uNrp 2.4.35.5/arch/i386/kernel/irq.c 2.4.35.5-i386-ipipe/arch/i386/kernel/irq.c
--- 2.4.35.5/arch/i386/kernel/irq.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/irq.c 2007-12-22 16:46:39.000000000 +0100
@@ -102,7 +102,7 @@ static void ack_none(unsigned int irq)
* unexpected vectors occur) that might lock up the APIC
* completely.
*/
- ack_APIC_irq();
+ __ack_APIC_irq();
#endif
#endif
}
@@ -444,6 +444,15 @@ int handle_IRQ_event(unsigned int irq, s
status = 1; /* Force the "do bottom halves" bit */
+#ifdef CONFIG_IPIPE
+ /* If processing a timer tick, pass the original regs as
+ collected during preemption and not our phony - always
+ kernel-originated - frame, so that we don't wreck the
+ profiling code. */
+ if (__ipipe_tick_irq == irq)
+ regs = __ipipe_tick_regs + smp_processor_id();
+#endif /* CONFIG_IPIPE */
+
if (!(action->flags & SA_INTERRUPT))
__sti();
@@ -595,7 +604,10 @@ asmlinkage unsigned int do_IRQ(struct pt
kstat.irqs[cpu][irq]++;
spin_lock(&desc->lock);
+#ifndef CONFIG_IPIPE
desc->handler->ack(irq);
+#endif /* CONFIG_IPIPE */
+
/*
REPLAY is when Linux resends an IRQ that was dropped earlier
WAITING is used by probe to mark irqs that are being tested
@@ -1213,3 +1225,27 @@ void init_irq_proc (void)
register_irq_proc(i);
}
+#if defined(CONFIG_IPIPE) && defined(CONFIG_SMP)
+
+cpumask_t __ipipe_set_irq_affinity (unsigned irq, cpumask_t cpumask)
+
+{
+ cpumask_t oldmask = irq_affinity[irq];
+
+ if (irq_desc[irq].handler->set_affinity == NULL)
+ return CPU_MASK_NONE;
+
+ if (cpus_empty(cpumask))
+ return oldmask; /* Return mask value -- no change. */
+
+ cpus_and(cpumask,cpumask,cpu_online_map);
+
+ if (cpus_empty(cpumask))
+ return CPU_MASK_NONE; /* Error -- bad mask value or non-routable IRQ. */
+
+ irq_affinity[irq] = cpumask;
+ irq_desc[irq].handler->set_affinity(irq,cpumask);
+ return oldmask;
+}
+
+#endif /* CONFIG_IPIPE && CONFIG_SMP */
diff -uNrp 2.4.35.5/arch/i386/kernel/nmi.c 2.4.35.5-i386-ipipe/arch/i386/kernel/nmi.c
--- 2.4.35.5/arch/i386/kernel/nmi.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/nmi.c 2007-12-22 16:46:39.000000000 +0100
@@ -29,6 +29,7 @@ unsigned int nmi_watchdog = NMI_NONE;
static unsigned int nmi_hz = HZ;
unsigned int nmi_perfctr_msr; /* the MSR to reset in NMI handler */
extern void show_registers(struct pt_regs *regs);
+static void default_nmi_watchdog_tick (struct pt_regs * regs);
#define K7_EVNTSEL_ENABLE (1 << 22)
#define K7_EVNTSEL_INT (1 << 20)
@@ -109,6 +110,7 @@ static int __init setup_nmi_watchdog(cha
if (nmi >= NMI_INVALID)
return 0;
+ nmi_watchdog_tick = default_nmi_watchdog_tick;
if (nmi == NMI_NONE)
nmi_watchdog = nmi;
/*
@@ -304,7 +306,7 @@ void __pminit setup_apic_nmi_watchdog (v
nmi_pm_init();
}
-static spinlock_t nmi_print_lock = SPIN_LOCK_UNLOCKED;
+spinlock_t nmi_print_lock = SPIN_LOCK_UNLOCKED;
/*
* the best way to detect whether a CPU has a 'hard lockup' problem
@@ -337,7 +339,7 @@ void touch_nmi_watchdog (void)
alert_counter[i] = 0;
}
-void nmi_watchdog_tick (struct pt_regs * regs)
+static void default_nmi_watchdog_tick (struct pt_regs * regs)
{
/*
diff -uNrp 2.4.35.5/arch/i386/kernel/process.c 2.4.35.5-i386-ipipe/arch/i386/kernel/process.c
--- 2.4.35.5/arch/i386/kernel/process.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/process.c 2007-12-22 16:46:39.000000000 +0100
@@ -134,6 +134,7 @@ void cpu_idle (void)
void (*idle)(void) = pm_idle;
if (!idle)
idle = default_idle;
+ ipipe_suspend_domain();
while (!current->need_resched)
idle();
schedule();
diff -uNrp 2.4.35.5/arch/i386/kernel/smp.c 2.4.35.5-i386-ipipe/arch/i386/kernel/smp.c
--- 2.4.35.5/arch/i386/kernel/smp.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/smp.c 2007-12-22 16:46:39.000000000 +0100
@@ -133,6 +133,9 @@ static inline void __send_IPI_shortcut(u
* to the APIC.
*/
unsigned int cfg;
+ unsigned long flags;
+
+ local_irq_save_hw_cond(flags);
/*
* Wait for idle.
@@ -148,6 +151,8 @@ static inline void __send_IPI_shortcut(u
* Send the IPI. The write to APIC_ICR fires this off.
*/
apic_write_around(APIC_ICR, cfg);
+
+ local_irq_restore_hw_cond(flags);
}
void fastcall send_IPI_self(int vector)
@@ -160,9 +165,8 @@ static inline void send_IPI_mask_bitmask
unsigned long cfg;
unsigned long flags;
- __save_flags(flags);
- __cli();
+ local_irq_save_hw(flags);
/*
* Wait for idle.
@@ -185,7 +189,7 @@ static inline void send_IPI_mask_bitmask
*/
apic_write_around(APIC_ICR, cfg);
- __restore_flags(flags);
+ local_irq_restore_hw(flags);
}
static inline void send_IPI_mask_sequence(int mask, int vector)
@@ -199,8 +203,7 @@ static inline void send_IPI_mask_sequenc
* should be modified to do 1 message per cluster ID - mbligh
*/
- __save_flags(flags);
- __cli();
+ local_irq_save_hw(flags);
for (query_cpu = 0; query_cpu < NR_CPUS; ++query_cpu) {
query_mask = 1 << query_cpu;
@@ -231,7 +234,7 @@ static inline void send_IPI_mask_sequenc
apic_write_around(APIC_ICR, cfg);
}
}
- __restore_flags(flags);
+ local_irq_restore_hw(flags);
}
static inline void send_IPI_mask(int mask, int vector)
@@ -360,8 +363,12 @@ static void inline leave_mm (unsigned lo
asmlinkage void smp_invalidate_interrupt (void)
{
- unsigned long cpu = smp_processor_id();
+ unsigned long cpu, flags;
+ local_irq_save_hw_cond(flags);
+
+ cpu = smp_processor_id();
+
if (!test_bit(cpu, &flush_cpumask))
return;
/*
@@ -384,6 +391,8 @@ asmlinkage void smp_invalidate_interrupt
}
ack_APIC_irq();
clear_bit(cpu, &flush_cpumask);
+
+ local_irq_restore_hw_cond(flags);
}
static void flush_tlb_others (unsigned long cpumask, struct mm_struct *mm,
@@ -434,10 +443,15 @@ void flush_tlb_current_task(void)
{
struct mm_struct *mm = current->mm;
unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id());
+ unsigned long flags;
+ local_irq_save_hw_cond(flags);
+
local_flush_tlb();
if (cpu_mask)
flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
+
+ local_irq_restore_hw_cond(flags);
}
void flush_tlb_mm (struct mm_struct * mm)
@@ -458,7 +472,10 @@ void flush_tlb_page(struct vm_area_struc
{
struct mm_struct *mm = vma->vm_mm;
unsigned long cpu_mask = mm->cpu_vm_mask & ~(1 << smp_processor_id());
+ unsigned long flags;
+ local_irq_save_hw_cond(flags);
+
if (current->active_mm == mm) {
if(current->mm)
__flush_tlb_one(va);
@@ -466,6 +483,8 @@ void flush_tlb_page(struct vm_area_struc
leave_mm(smp_processor_id());
}
+ local_irq_restore_hw_cond(flags);
+
if (cpu_mask)
flush_tlb_others(cpu_mask, mm, va);
}
@@ -629,3 +648,34 @@ asmlinkage void smp_call_function_interr
}
}
+#if defined(CONFIG_IPIPE) && defined(CONFIG_SMP)
+
+int fastcall __ipipe_send_ipi(unsigned ipi, cpumask_t cpumask)
+
+{
+ unsigned long flags;
+ ipipe_declare_cpuid;
+ int self;
+
+ ipipe_lock_cpu(flags);
+
+ self = cpu_isset(cpuid,cpumask);
+ cpu_clear(cpuid,cpumask);
+
+ if (!cpus_empty(cpumask))
+ send_IPI_mask(cpumask,ipi + FIRST_EXTERNAL_VECTOR);
+
+ if (self)
+ ipipe_trigger_irq(ipi);
+
+ ipipe_unlock_cpu(flags);
+
+ return 0;
+}
+
+void __ipipe_send_IPI_allbutself (int vector)
+{
+ send_IPI_allbutself(vector);
+}
+
+#endif /* CONFIG_IPIPE && CONFIG_SMP */
diff -uNrp 2.4.35.5/arch/i386/kernel/smpboot.c 2.4.35.5-i386-ipipe/arch/i386/kernel/smpboot.c
--- 2.4.35.5/arch/i386/kernel/smpboot.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/smpboot.c 2007-12-22 16:46:39.000000000 +0100
@@ -776,6 +776,7 @@ static void __init do_boot_cpu (int apic
unsigned short nmi_high = 0, nmi_low = 0;
cpu = ++cpucount;
+ ipipe_note_apicid(apicid,cpu);
/*
* We can't use kernel_thread since we must avoid to
* reschedule the child.
@@ -1012,6 +1013,7 @@ void __init smp_boot_cpus(void)
else
boot_cpu_logical_apicid = logical_smp_processor_id();
map_cpu_to_boot_apicid(0, boot_cpu_apicid);
+ ipipe_note_apicid(boot_cpu_physical_apicid,0);
global_irq_holder = 0;
current->processor = 0;
diff -uNrp 2.4.35.5/arch/i386/kernel/time.c 2.4.35.5-i386-ipipe/arch/i386/kernel/time.c
--- 2.4.35.5/arch/i386/kernel/time.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/time.c 2007-12-22 16:46:39.000000000 +0100
@@ -167,6 +167,10 @@ static unsigned long do_slow_gettimeoffs
*/
unsigned long jiffies_t;
+#ifdef CONFIG_IPIPE
+ if (!__ipipe_pipeline_head_p(ipipe_root_domain))
+ return 0; /* We don't really own the PIT. */
+#endif /* CONFIG_IPIPE */
/* gets recalled with irq locally disabled */
spin_lock(&i8253_lock);
/* timer count may underflow right here */
@@ -210,14 +214,15 @@ static unsigned long do_slow_gettimeoffs
/* the nutcase */
int i;
+ unsigned long flags;
+ spin_lock_irqsave_hw_cond(&i8259A_lock,flags);
- spin_lock(&i8259A_lock);
/*
* This is tricky when I/O APICs are used;
* see do_timer_interrupt().
*/
i = inb(0x20);
- spin_unlock(&i8259A_lock);
+ spin_unlock_irqrestore_hw_cond(&i8259A_lock,flags);
/* assumption about timer being IRQ0 */
if (i & 0x01) {
@@ -281,6 +286,10 @@ static inline void mark_timeoffset_cyclo
int count;
unsigned long lost;
unsigned long delta = last_cyclone_timer;
+#ifdef CONFIG_IPIPE
+ if (!__ipipe_pipeline_head_p(ipipe_root_domain))
+ return; /* We don't really own the PIT. */
+#endif /* CONFIG_IPIPE */
spin_lock(&i8253_lock);
/* quickly read the cyclone timer */
if(cyclone_timer)
@@ -309,6 +318,10 @@ static unsigned long do_gettimeoffset_cy
{
u32 offset;
+#ifdef CONFIG_IPIPE
+ if (!__ipipe_pipeline_head_p(ipipe_root_domain))
+ return 0;
+#endif /* CONFIG_IPIPE */
if(!cyclone_timer)
return delay_at_last_interrupt;
@@ -577,14 +590,15 @@ static inline void do_timer_interrupt(in
* This will also deassert NMI lines for the watchdog if run
* on an 82489DX-based system.
*/
- spin_lock(&i8259A_lock);
+ unsigned long flags;
+ spin_lock_irqsave_hw_cond(&i8259A_lock,flags);
outb(0x0c, 0x20);
/* Ack the IRQ; AEOI will end it automatically. */
inb(0x20);
- spin_unlock(&i8259A_lock);
+ spin_unlock_irqrestore_hw_cond(&i8259A_lock,flags);
}
#endif
-
+
#ifdef CONFIG_VISWS
/* Clear the interrupt */
co_cpu_write(CO_CPU_STAT,co_cpu_read(CO_CPU_STAT) & ~CO_STAT_TIMEINTR);
@@ -644,8 +658,10 @@ static int use_tsc;
*/
static void timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
+#ifndef CONFIG_IPIPE
int count;
-
+#endif /* CONFIG_IPIPE */
+
/*
* Here we are in the timer irq handler. We just have irqs locally
* disabled but we don't know if the timer_bh is running on the other
@@ -674,6 +690,7 @@ static void timer_interrupt(int irq, voi
rdtscl(last_tsc_low);
+#ifndef CONFIG_IPIPE
spin_lock(&i8253_lock);
outb_p(0x00, 0x43); /* latch the count ASAP */
@@ -705,6 +722,8 @@ static void timer_interrupt(int irq, voi
count = ((LATCH-1) - count) * TICK_SIZE;
delay_at_last_interrupt = (count + LATCH/2) / LATCH;
+
+#endif /* CONFIG_IPIPE */
}
do_timer_interrupt(irq, NULL, regs);
diff -uNrp 2.4.35.5/arch/i386/kernel/traps.c 2.4.35.5-i386-ipipe/arch/i386/kernel/traps.c
--- 2.4.35.5/arch/i386/kernel/traps.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/kernel/traps.c 2007-12-22 16:46:39.000000000 +0100
@@ -216,6 +216,11 @@ void show_registers(struct pt_regs *regs
regs->esi, regs->edi, regs->ebp, esp);
printk("ds: %04x es: %04x ss: %04x\n",
regs->xds & 0xffff, regs->xes & 0xffff, ss);
+#ifdef CONFIG_IPIPE
+ if (ipipe_current_domain != ipipe_root_domain)
+ printk("I-pipe domain %s",ipipe_current_domain->name);
+ else
+#endif /* CONFIG_IPIPE */
printk("Process %s (pid: %d, stackpage=%08lx)",
current->comm, current->pid, 4096+(unsigned long)current);
/*
@@ -753,6 +758,10 @@ asmlinkage void do_spurious_interrupt_bu
*/
asmlinkage void math_state_restore(struct pt_regs regs)
{
+ unsigned long flags;
+
+ local_irq_save_hw_cond(flags);
+
__asm__ __volatile__("clts"); /* Allow maths ops (or we recurse) */
if (current->used_math) {
@@ -761,6 +770,8 @@ asmlinkage void math_state_restore(struc
init_fpu();
}
current->flags |= PF_USEDFPU; /* So we fnsave on switch_to() */
+
+ local_irq_restore_hw_cond(flags);
}
#ifndef CONFIG_MATH_EMULATION
diff -uNrp 2.4.35.5/arch/i386/lib/mmx.c 2.4.35.5-i386-ipipe/arch/i386/lib/mmx.c
--- 2.4.35.5/arch/i386/lib/mmx.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/lib/mmx.c 2007-12-22 16:46:39.000000000 +0100
@@ -31,7 +31,7 @@ void *_mmx_memcpy(void *to, const void *
void *p;
int i;
- if (in_interrupt())
+ if (unlikely(!ipipe_root_domain_p || in_interrupt()))
return __memcpy(to, from, len);
p = to;
diff -uNrp 2.4.35.5/arch/i386/mm/fault.c 2.4.35.5-i386-ipipe/arch/i386/mm/fault.c
--- 2.4.35.5/arch/i386/mm/fault.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/mm/fault.c 2007-12-22 16:46:39.000000000 +0100
@@ -151,6 +151,8 @@ asmlinkage void do_page_fault(struct pt_
/* get the address */
__asm__("movl %%cr2,%0":"=r" (address));
+ local_irq_enable_hw_cond();
+
/* It's safe to allow irq's after cr2 has been saved */
if (regs->eflags & X86_EFLAGS_IF)
local_irq_enable();
diff -uNrp 2.4.35.5/arch/i386/mm/ioremap.c 2.4.35.5-i386-ipipe/arch/i386/mm/ioremap.c
--- 2.4.35.5/arch/i386/mm/ioremap.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/arch/i386/mm/ioremap.c 2007-12-22 16:46:39.000000000 +0100
@@ -81,6 +81,7 @@ static int remap_area_pages(unsigned lon
if (remap_area_pmd(pmd, address, end - address,
phys_addr + address, flags))
break;
+ set_pgdir(address, *dir);
error = 0;
address = (address + PGDIR_SIZE) & PGDIR_MASK;
dir++;
diff -uNrp 2.4.35.5/include/asm-i386/apic.h 2.4.35.5-i386-ipipe/include/asm-i386/apic.h
--- 2.4.35.5/include/asm-i386/apic.h 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/asm-i386/apic.h 2007-12-22 16:48:48.000000000 +0100
@@ -50,7 +50,13 @@ static __inline__ void apic_wait_icr_idl
# define apic_write_around(x,y) apic_write_atomic((x),(y))
#endif
+#ifdef CONFIG_IPIPE
+#define ack_APIC_irq() do { } while(0)
+static inline void __ack_APIC_irq(void)
+#else /* !CONFIG_IPIPE */
+#define __ack_APIC_irq() ack_APIC_irq()
static inline void ack_APIC_irq(void)
+#endif /* CONFIG_IPIPE */
{
/*
* ack_APIC_irq() actually gets compiled as a single instruction:
@@ -77,7 +83,7 @@ extern void init_apic_mappings (void);
extern void smp_local_timer_interrupt (struct pt_regs * regs);
extern void setup_APIC_clocks (void);
extern void setup_apic_nmi_watchdog (void);
-extern void nmi_watchdog_tick (struct pt_regs * regs);
+extern void (*nmi_watchdog_tick) (struct pt_regs * regs);
extern int APIC_init_uniprocessor (void);
extern void disable_APIC_timer(void);
extern void enable_APIC_timer(void);
diff -uNrp 2.4.35.5/include/asm-i386/hw_irq.h 2.4.35.5-i386-ipipe/include/asm-i386/hw_irq.h
--- 2.4.35.5/include/asm-i386/hw_irq.h 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/asm-i386/hw_irq.h 2007-12-22 16:47:48.000000000 +0100
@@ -123,6 +123,37 @@ extern char _stext, _etext;
/* there is a second layer of macro just to get the symbolic
name for the vector evaluated. This change is for RTLinux */
+
+#ifdef CONFIG_IPIPE
+
+#define BUILD_SMP_INTERRUPT(x,v) XBUILD_SMP_INTERRUPT(x,v)
+#define BUILD_SMP_TIMER_INTERRUPT(x,v) XBUILD_SMP_INTERRUPT(x,v)
+#define XBUILD_SMP_INTERRUPT(x,v)\
+asmlinkage void x(void); \
+asmlinkage void call_##x(void); \
+__asm__( \
+"\n"__ALIGN_STR"\n" \
+SYMBOL_NAME_STR(x) ":\n\t" \
+ "pushl $"#v"-288\n\t" /* nr - (256 + FIRST_EXTERNAL_VECTOR) */ \
+ SAVE_ALL \
+ "call *"SYMBOL_NAME_STR(ipipe_irq_handler)"\n\t" \
+ "testl %eax,%eax\n\t" \
+ "jnz ret_from_intr\n\t" \
+ "jmp restore_raw\n");
+
+#define BUILD_COMMON_IRQ() \
+asmlinkage void call_do_IRQ(void); \
+__asm__( \
+ "\n" __ALIGN_STR"\n" \
+ "common_interrupt:\n\t" \
+ SAVE_ALL \
+ "call *"SYMBOL_NAME_STR(ipipe_irq_handler)"\n\t" \
+ "testl %eax,%eax\n\t" \
+ "jnz ret_from_intr\n\t" \
+ "jmp restore_raw\n");
+
+#else /* !CONFIG_IPIPE */
+
#define BUILD_SMP_INTERRUPT(x,v) XBUILD_SMP_INTERRUPT(x,v)
#define XBUILD_SMP_INTERRUPT(x,v)\
asmlinkage void x(void); \
@@ -162,6 +193,8 @@ __asm__( \
"call " SYMBOL_NAME_STR(do_IRQ) "\n\t" \
"jmp ret_from_intr\n");
+#endif /* CONFIG_IPIPE */
+
/*
* subtle. orig_eax is used by the signal code to distinct between
* system calls and interrupted 'random user-space'. Thus we have
diff -uNrp 2.4.35.5/include/asm-i386/ipipe.h 2.4.35.5-i386-ipipe/include/asm-i386/ipipe.h
--- 2.4.35.5/include/asm-i386/ipipe.h 1970-01-01 01:00:00.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/asm-i386/ipipe.h 2007-12-22 16:48:48.000000000 +0100
@@ -0,0 +1,281 @@
+/* -*- linux-c -*-
+ * include/asm-i386/ipipe.h
+ *
+ * Copyright (C) 2002-2005 Philippe Gerum.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __I386_IPIPE_H
+#define __I386_IPIPE_H
+
+#include <linux/config.h>
+
+#ifdef CONFIG_IPIPE
+
+#ifndef __ASSEMBLY__
+#include <asm/irq.h>
+#endif /* __ASSEMBLY__ */
+
+#define IPIPE_ARCH_STRING "1.3-04"
+#define IPIPE_MAJOR_NUMBER 1
+#define IPIPE_MINOR_NUMBER 3
+#define IPIPE_PATCH_NUMBER 4
+
+#define __clear_bit(nr,addr) clear_bit(nr,addr)
+#define __test_bit(nr,addr) test_bit(nr,addr)
+
+#ifdef CONFIG_X86_LOCAL_APIC
+/* We want to cover the whole IRQ space when the APIC is enabled. */
+#ifdef CONFIG_PCI_MSI
+#define IPIPE_NR_XIRQS NR_IRQS
+#else /* CONFIG_PCI_MSI */
+#define IPIPE_NR_XIRQS 224
+#endif /* CONFIG_PCI_MSI */
+/* If the APIC is enabled, then we expose four service vectors in the
+ APIC space which are freely available to domains. */
+#define IPIPE_SERVICE_VECTOR0 0xf5
+#define IPIPE_SERVICE_IPI0 (IPIPE_SERVICE_VECTOR0 - FIRST_EXTERNAL_VECTOR)
+#define IPIPE_SERVICE_VECTOR1 0xf6
+#define IPIPE_SERVICE_IPI1 (IPIPE_SERVICE_VECTOR1 - FIRST_EXTERNAL_VECTOR)
+#define IPIPE_SERVICE_VECTOR2 0xf7
+#define IPIPE_SERVICE_IPI2 (IPIPE_SERVICE_VECTOR2 - FIRST_EXTERNAL_VECTOR)
+#define IPIPE_SERVICE_VECTOR3 0xf8
+#define IPIPE_SERVICE_IPI3 (IPIPE_SERVICE_VECTOR3 - FIRST_EXTERNAL_VECTOR)
+#else /* !CONFIG_X86_LOCAL_APIC */
+#define IPIPE_NR_XIRQS NR_IRQS
+#endif /* CONFIG_X86_LOCAL_APIC */
+
+#define IPIPE_IRQ_ISHIFT 5 /* 2^5 for 32bits arch. */
+#define NR_XIRQS IPIPE_NR_XIRQS
+
+#define ex_do_divide_error 0
+#define ex_do_debug 1
+/* NMI not pipelined. */
+#define ex_do_int3 3
+#define ex_do_overflow 4
+#define ex_do_bounds 5
+#define ex_do_invalid_op 6
+#define ex_device_not_available 7
+#define ex_do_double_fault 8
+#define ex_do_coprocessor_segment_overrun 9
+#define ex_do_invalid_TSS 10
+#define ex_do_segment_not_present 11
+#define ex_do_stack_segment 12
+#define ex_do_general_protection 13
+#define ex_do_page_fault 14
+#define ex_do_spurious_interrupt_bug 15
+#define ex_do_coprocessor_error 16
+#define ex_do_alignment_check 17
+#define ex_do_machine_check 18
+#define ex_do_simd_coprocessor_error 19
+
+#ifndef __ASSEMBLY__
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/threads.h>
+#include <asm/ptrace.h>
+
+#ifdef CONFIG_SMP
+
+#include <asm/fixmap.h>
+#include <asm/mpspec.h>
+
+#define IPIPE_CRITICAL_VECTOR 0xf9 /* Used by ipipe_critical_enter/exit() */
+#define IPIPE_CRITICAL_IPI (IPIPE_CRITICAL_VECTOR - FIRST_EXTERNAL_VECTOR)
+
+static inline int ipipe_processor_id(void)
+{
+ extern int (*__ipipe_logical_cpuid)(void);
+ return __ipipe_logical_cpuid();
+}
+
+extern u8 __ipipe_apicid_2_cpu[];
+
+#define ipipe_note_apicid(apicid,cpu) \
+do { \
+ __ipipe_apicid_2_cpu[apicid] = cpu; \
+} while(0)
+
+#define task_hijacked(p) \
+ ({ int __x__ = ipipe_current_domain != ipipe_root_domain; \
+ __clear_bit(IPIPE_SYNC_FLAG,&ipipe_root_domain->cpudata[smp_processor_id()].status); \
+ local_irq_enable_hw(); __x__; })
+
+#else /* !CONFIG_SMP */
+
+#define ipipe_note_apicid(apicid,cpu) do { } while(0)
+#define ipipe_processor_id() 0
+
+#define task_hijacked(p) \
+ ({ int __x__ = ipipe_current_domain != ipipe_root_domain; \
+ local_irq_enable_hw(); __x__; })
+
+#endif /* CONFIG_SMP */
+
+#define prepare_to_switch(next) \
+do { \
+ ipipe_schedule_notify(current ,next); \
+ local_irq_disable_hw(); \
+} while(0)
+
+/* IDT fault vectors */
+#define IPIPE_NR_FAULTS 32 /* 32 from IDT */
+/* Pseudo-vectors used for kernel events */
+#define IPIPE_FIRST_EVENT IPIPE_NR_FAULTS
+#define IPIPE_EVENT_SYSCALL (IPIPE_FIRST_EVENT)
+#define IPIPE_EVENT_SCHEDULE (IPIPE_FIRST_EVENT + 1)
+#define IPIPE_EVENT_SIGWAKE (IPIPE_FIRST_EVENT + 2)
+#define IPIPE_EVENT_SETSCHED (IPIPE_FIRST_EVENT + 3)
+#define IPIPE_EVENT_INIT (IPIPE_FIRST_EVENT + 4)
+#define IPIPE_EVENT_EXIT (IPIPE_FIRST_EVENT + 5)
+#define IPIPE_EVENT_CLEANUP (IPIPE_FIRST_EVENT + 6)
+#define IPIPE_LAST_EVENT IPIPE_EVENT_CLEANUP
+#define IPIPE_NR_EVENTS (IPIPE_LAST_EVENT + 1)
+
+struct ipipe_domain;
+
+struct ipipe_sysinfo {
+
+ int ncpus; /* Number of CPUs on board */
+ u64 cpufreq; /* CPU frequency (in Hz) */
+
+ /* Arch-dependent block */
+
+ struct {
+ unsigned tmirq; /* Timer tick IRQ */
+ u64 tmfreq; /* Timer frequency */
+ } archdep;
+};
+
+#define ipipe_read_tsc(t) __asm__ __volatile__("rdtsc" : "=A" (t))
+#define ipipe_cpu_freq() ({ unsigned long long __freq = cpu_has_tsc?(1000LL * cpu_khz):CLOCK_TICK_RATE; __freq; })
+#define ipipe_tsc2ns(t) (((t) * 1000) / (cpu_khz / 1000))
+
+/* Private interface -- Internal use only */
+
+#define __ipipe_check_platform() do { } while(0)
+
+#define __ipipe_init_platform() do { } while(0)
+
+#define __ipipe_enable_irqdesc(irq) do { irq_desc[irq].status &= ~IRQ_DISABLED; } while(0)
+
+#define __ipipe_enable_irq(irq) irq_desc[irq].handler->enable(irq)
+
+#define __ipipe_disable_irq(irq) irq_desc[irq].handler->disable(irq)
+
+void __ipipe_enable_pipeline(void);
+
+int __ipipe_ack_system_irq(unsigned irq);
+
+int __ipipe_handle_irq(struct pt_regs regs);
+
+void __ipipe_do_critical_sync(unsigned irq, void *cookie);
+
+extern struct pt_regs __ipipe_tick_regs[];
+
+extern int __ipipe_tick_irq;
+
+#define __ipipe_call_root_xirq_handler(ipd,irq) \
+ __asm__ __volatile__ ("pushfl\n\t" \
+ "pushl %%cs\n\t" \
+ "pushl $1f\n\t" \
+ "pushl %%eax\n\t" \
+ "pushl %%es\n\t" \
+ "pushl %%ds\n\t" \
+ "pushl %%eax\n\t" \
+ "pushl %%ebp\n\t" \
+ "pushl %%edi\n\t" \
+ "pushl %%esi\n\t" \
+ "pushl %%edx\n\t" \
+ "pushl %%ecx\n\t" \
+ "pushl %%ebx\n\t" \
+ "movl %%esp,%%eax\n\t" \
+ "call *%1\n\t" \
+ "jmp ret_from_intr\n\t" \
+ "1:\n" \
+ : /* no output */ \
+ : "a" (irq-256), "m" ((ipd)->irqs[irq].handler))
+
+#define __ipipe_call_root_virq_handler(ipd,irq) \
+ __asm__ __volatile__ ("pushfl\n\t" \
+ "pushl %%cs\n\t" \
+ "pushl $1f\n\t" \
+ "pushl $-1\n\t" \
+ "pushl %%es\n\t" \
+ "pushl %%ds\n\t" \
+ "pushl %%eax\n\t" \
+ "pushl %%ebp\n\t" \
+ "pushl %%edi\n\t" \
+ "pushl %%esi\n\t" \
+ "pushl %%edx\n\t" \
+ "pushl %%ecx\n\t" \
+ "pushl %%ebx\n\t" \
+ "pushl %2\n\t" \
+ "pushl %%eax\n\t" \
+ "call *%1\n\t" \
+ "addl $8,%%esp\n\t" \
+ "jmp ret_from_intr\n\t" \
+ "1:\n" \
+ : /* no output */ \
+ : "a" (irq), "m" ((ipd)->irqs[irq].handler), "d" ((ipd)->irqs[irq].cookie))
+
+static inline unsigned long __ipipe_ffnz(unsigned long ul)
+{
+ __asm__("bsrl %1, %0":"=r"(ul)
+ : "r"(ul));
+ return ul;
+}
+
+/* When running handlers, enable hw interrupts for all domains but the
+ * one heading the pipeline, so that IRQs can never be significantly
+ * deferred for the latter. */
+#define __ipipe_run_isr(ipd, irq, cpuid) \
+do { \
+ local_irq_enable_nohead(ipd); \
+ if (ipd == ipipe_root_domain) { \
+ if (likely(!ipipe_virtual_irq_p(irq))) { \
+ __ipipe_call_root_xirq_handler(ipd,irq); \
+ } else { \
+ irq_enter(cpuid, irq); \
+ __ipipe_call_root_virq_handler(ipd,irq); \
+ irq_exit(cpuid, irq); \
+ } \
+ } else { \
+ __clear_bit(IPIPE_SYNC_FLAG, &cpudata->status); \
+ ipd->irqs[irq].handler(irq, ipd->irqs[irq].cookie); \
+ __set_bit(IPIPE_SYNC_FLAG, &cpudata->status); \
+ } \
+ local_irq_disable_nohead(ipd); \
+} while(0)
+
+#define __ipipe_syscall_watched_p(p, sc) \
+ (((p)->flags & PF_EVNOTIFY) || (unsigned long)sc >= NR_syscalls)
+
+#endif /* __ASSEMBLY__ */
+
+#else /* !CONFIG_IPIPE */
+
+#define task_hijacked(p) 0
+
+#define NR_XIRQS NR_IRQS
+
+#define ipipe_note_apicid(apicid,cpu) do { } while(0)
+
+#endif /* CONFIG_IPIPE */
+
+#endif /* !__I386_IPIPE_H */
diff -uNrp 2.4.35.5/include/asm-i386/mmu_context.h 2.4.35.5-i386-ipipe/include/asm-i386/mmu_context.h
--- 2.4.35.5/include/asm-i386/mmu_context.h 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/asm-i386/mmu_context.h 2007-12-22 16:47:49.000000000 +0100
@@ -62,6 +62,11 @@ static inline void switch_mm(struct mm_s
}
#define activate_mm(prev, next) \
- switch_mm((prev),(next),NULL,smp_processor_id())
-
+do { \
+ unsigned long flags; \
+ local_irq_save_hw_cond(flags); \
+ switch_mm((prev),(next),NULL,smp_processor_id()); \
+ local_irq_restore_hw_cond(flags); \
+} while(0)
+
#endif
diff -uNrp 2.4.35.5/include/asm-i386/pgalloc.h 2.4.35.5-i386-ipipe/include/asm-i386/pgalloc.h
--- 2.4.35.5/include/asm-i386/pgalloc.h 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/asm-i386/pgalloc.h 2007-12-22 16:48:48.000000000 +0100
@@ -235,4 +235,40 @@ static inline void flush_tlb_pgtables(st
flush_tlb_mm(mm);
}
+/* Non-root Ipipe domains cannot might not cope with on-demand
+ mappings for I/O or vmalloc'ed memory, so fall back to a brute
+ force instantaneous kernel global mapping of these areas. */
+
+static inline void set_pgdir(unsigned long address, pgd_t entry)
+{
+#ifdef CONFIG_IPIPE
+ struct task_struct *p;
+ pgd_t *pgd;
+
+ read_lock(&tasklist_lock);
+ for_each_task(p) {
+ if (!p->mm)
+ continue;
+ *pgd_offset(p->mm,address) = entry;
+ }
+ read_unlock(&tasklist_lock);
+#ifdef CONFIG_SMP
+ {
+ int cpu;
+ /* To pgd_alloc/pgd_free, one holds the page table lock and so
+ does our callee, so we can modify pgd caches of other CPUs
+ as well. -jj +rpm*/
+ for (cpu = 0; cpu < NR_CPUS; cpu++)
+ for (pgd = (pgd_t *)cpu_data[cpu].pgd_quick; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
+ pgd[address >> PGDIR_SHIFT] = entry;
+ }
+#else /* !CONFIG_SMP */
+ for (pgd = (pgd_t *)pgd_quicklist; pgd; pgd = (pgd_t *)*(unsigned long *)pgd)
+ pgd[address >> PGDIR_SHIFT] = entry;
+#endif /* CONFIG_SMP */
+#endif /* CONFIG_IPIPE */
+}
+
+
+
#endif /* _I386_PGALLOC_H */
diff -uNrp 2.4.35.5/include/asm-i386/system.h 2.4.35.5-i386-ipipe/include/asm-i386/system.h
--- 2.4.35.5/include/asm-i386/system.h 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/asm-i386/system.h 2007-12-22 16:48:48.000000000 +0100
@@ -12,7 +12,10 @@
struct task_struct; /* one of the stranger aspects of C forward declarations.. */
extern void FASTCALL(__switch_to(struct task_struct *prev, struct task_struct *next));
-#define prepare_to_switch() do { } while(0)
+#ifndef CONFIG_IPIPE
+#define prepare_to_switch(next) do { } while(0)
+#endif /* CONFIG_IPIPE */
+
#define switch_to(prev,next,last) do { \
asm volatile("pushl %%esi\n\t" \
"pushl %%edi\n\t" \
@@ -313,6 +316,51 @@ static inline unsigned long __cmpxchg(vo
#define set_wmb(var, value) do { var = value; wmb(); } while (0)
/* interrupt control.. */
+#ifdef CONFIG_IPIPE
+
+#include <linux/linkage.h>
+
+void __ipipe_stall_root(void);
+void __ipipe_unstall_root(void);
+unsigned long __ipipe_test_root(void);
+unsigned long __ipipe_test_and_stall_root(void);
+void FASTCALL(__ipipe_restore_root(unsigned long flags));
+
+#define __save_flags(x) ((x) = (!__ipipe_test_root()) << 9)
+#define __restore_flags(x) __ipipe_restore_root(!(x & 0x200))
+#define __cli() __ipipe_stall_root()
+#define __sti() __ipipe_unstall_root()
+
+#define safe_halt() do { \
+ __ipipe_unstall_root(); \
+ __asm__ __volatile__("sti; hlt": : :"memory"); \
+} while(0)
+
+#define __save_and_cli(x) do { __save_flags(x); __cli(); } while(0);
+#define __save_and_sti(x) do { __save_flags(x); __sti(); } while(0);
+
+#define local_irq_save(x) __save_and_cli(x)
+#define local_irq_set(x) __save_and_sti(x)
+
+#define local_irq_restore(x) __restore_flags(x)
+#define local_irq_disable() __cli()
+#define local_irq_enable() __sti()
+
+#define local_irq_disable_hw() __asm__ __volatile__("cli": : :"memory")
+#define local_irq_enable_hw() __asm__ __volatile__("sti": : :"memory")
+#define local_irq_save_hw(x) __asm__ __volatile__("pushfl ; popl %0 ; cli":"=g" (x): /* no input */ :"memory")
+#define local_irq_restore_hw(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc")
+#define local_save_flags_hw(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
+#define local_test_iflag_hw(x) ((x) & (1<<9))
+#define irqs_disabled_hw() \
+({ \
+ unsigned long flags; \
+ local_save_flags_hw(flags); \
+ !local_test_iflag_hw(flags); \
+})
+
+#else /* !CONFIG_IPIPE */
+
#define __save_flags(x) __asm__ __volatile__("pushfl ; popl %0":"=g" (x): /* no input */)
#define __restore_flags(x) __asm__ __volatile__("pushl %0 ; popfl": /* no output */ :"g" (x):"memory", "cc")
#define __cli() __asm__ __volatile__("cli": : :"memory")
@@ -336,6 +384,13 @@ static inline unsigned long __cmpxchg(vo
#define local_irq_disable() __cli()
#define local_irq_enable() __sti()
+#define local_irq_save_hw(flags) local_irq_save(flags)
+#define local_irq_restore_hw(flags) local_irq_restore(flags)
+#define local_irq_enable_hw() local_irq_enable()
+#define local_irq_disable_hw(flags) local_irq_disable()
+
+#endif /* CONFIG_IPIPE */
+
#ifdef CONFIG_SMP
extern void __global_cli(void);
diff -uNrp 2.4.35.5/include/linux/ipipe.h 2.4.35.5-i386-ipipe/include/linux/ipipe.h
--- 2.4.35.5/include/linux/ipipe.h 1970-01-01 01:00:00.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/linux/ipipe.h 2007-12-22 16:48:48.000000000 +0100
@@ -0,0 +1,760 @@
+/* -*- linux-c -*-
+ * include/linux/ipipe.h
+ *
+ * Copyright (C) 2002-2005 Philippe Gerum.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __LINUX_IPIPE_H
+#define __LINUX_IPIPE_H
+
+#include <linux/config.h>
+#include <linux/spinlock.h>
+#include <linux/cache.h>
+#include <asm/ipipe.h>
+
+#ifdef CONFIG_IPIPE
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/smp.h>
+
+#define IPIPE_VERSION_STRING IPIPE_ARCH_STRING
+#define IPIPE_RELEASE_NUMBER ((IPIPE_MAJOR_NUMBER << 16) | \
+ (IPIPE_MINOR_NUMBER << 8) | \
+ (IPIPE_PATCH_NUMBER))
+
+#define IPIPE_ROOT_PRIO 100
+#define IPIPE_ROOT_ID 0
+#define IPIPE_ROOT_NPTDKEYS 4 /* Must be <= BITS_PER_LONG */
+
+#define IPIPE_RESET_TIMER 0x1
+#define IPIPE_GRAB_TIMER 0x2
+
+/* Global domain flags */
+#define IPIPE_SPRINTK_FLAG 0 /* Synchronous printk() allowed */
+#define IPIPE_AHEAD_FLAG 1 /* Domain always heads the pipeline */
+
+#define IPIPE_STALL_FLAG 0 /* Stalls a pipeline stage -- guaranteed at bit #0 */
+#define IPIPE_SYNC_FLAG 1 /* The interrupt syncer is running for the domain */
+#define IPIPE_NOSTACK_FLAG 2 /* Domain currently runs on a foreign stack */
+
+#define IPIPE_SYNC_MASK (1 << IPIPE_SYNC_FLAG)
+
+#define IPIPE_HANDLE_FLAG 0
+#define IPIPE_PASS_FLAG 1
+#define IPIPE_ENABLE_FLAG 2
+#define IPIPE_DYNAMIC_FLAG IPIPE_HANDLE_FLAG
+#define IPIPE_STICKY_FLAG 3
+#define IPIPE_SYSTEM_FLAG 4
+#define IPIPE_LOCK_FLAG 5
+#define IPIPE_SHARED_FLAG 6
+#define IPIPE_WIRED_FLAG 7
+#define IPIPE_EXCLUSIVE_FLAG 8
+
+#define IPIPE_HANDLE_MASK (1 << IPIPE_HANDLE_FLAG)
+#define IPIPE_PASS_MASK (1 << IPIPE_PASS_FLAG)
+#define IPIPE_ENABLE_MASK (1 << IPIPE_ENABLE_FLAG)
+#define IPIPE_DYNAMIC_MASK IPIPE_HANDLE_MASK
+#define IPIPE_STICKY_MASK (1 << IPIPE_STICKY_FLAG)
+#define IPIPE_SYSTEM_MASK (1 << IPIPE_SYSTEM_FLAG)
+#define IPIPE_LOCK_MASK (1 << IPIPE_LOCK_FLAG)
+#define IPIPE_SHARED_MASK (1 << IPIPE_SHARED_FLAG)
+#define IPIPE_WIRED_MASK (1 << IPIPE_WIRED_FLAG)
+#define IPIPE_EXCLUSIVE_MASK (1 << IPIPE_EXCLUSIVE_FLAG)
+
+#define IPIPE_DEFAULT_MASK (IPIPE_HANDLE_MASK|IPIPE_PASS_MASK)
+#define IPIPE_STDROOT_MASK (IPIPE_HANDLE_MASK|IPIPE_PASS_MASK|IPIPE_SYSTEM_MASK)
+
+#define IPIPE_EVENT_SELF 0x80000000
+
+/* Number of virtual IRQs */
+#define IPIPE_NR_VIRQS BITS_PER_LONG
+/* First virtual IRQ # */
+#define IPIPE_VIRQ_BASE (((IPIPE_NR_XIRQS + BITS_PER_LONG - 1) / BITS_PER_LONG) * BITS_PER_LONG)
+/* Total number of IRQ slots */
+#define IPIPE_NR_IRQS (IPIPE_VIRQ_BASE + IPIPE_NR_VIRQS)
+/* Number of indirect words needed to map the whole IRQ space. */
+#define IPIPE_IRQ_IWORDS ((IPIPE_NR_IRQS + BITS_PER_LONG - 1) / BITS_PER_LONG)
+#define IPIPE_IRQ_IMASK (BITS_PER_LONG - 1)
+#define IPIPE_IRQMASK_ANY (~0L)
+#define IPIPE_IRQMASK_VIRT (IPIPE_IRQMASK_ANY << (IPIPE_VIRQ_BASE / BITS_PER_LONG))
+
+typedef unsigned long cpumask_t;
+
+#define cpus_andnot(dst,src1,src2) ((dst) = (src1) & ~(src2))
+#define cpus_and(dst,src1,src2) ((dst) = (src1) & (src2))
+#define cpus_equal(src1,src2) ((src1) == (src2))
+#define cpus_empty(src) ((src) == 0)
+#define cpus_clear(dst) ((dst) = 0)
+#define cpus_weight(src) hweight32(src)
+#define cpu_clear(cpu,dst) ((dst) &= ~(1UL << (cpu)))
+#define cpu_isset(cpu,src) ((src) & (1UL << (cpu)))
+#define cpu_set(cpu,dst) ((dst) |= (1UL << (cpu)))
+#define cpumask_of_cpu(cpu) (1UL << (cpu))
+#define cpu_test_and_set(cpu,dst) test_and_set_bit(cpu,&dst)
+#define cpu_test_and_clear(cpu,dst) test_and_clear_bit(cpu,&dst)
+#define first_cpu(src) (ffs(src) - 1)
+
+#define num_online_cpus() smp_num_cpus
+#define CPU_MASK_NONE 0
+#define CPU_MASK_ALL (~0)
+#define for_each_online_cpu(cpu) for ((cpu) = 0; (cpu) < NR_CPUS; (cpu)++) \
+ if (cpu_isset(cpu,cpu_online_map))
+
+#ifdef CONFIG_SMP
+
+#define IPIPE_NR_CPUS NR_CPUS
+#define ipipe_declare_cpuid int cpuid
+#define ipipe_load_cpuid() do { \
+ (cpuid) = ipipe_processor_id(); \
+ } while(0)
+#define ipipe_lock_cpu(flags) do { \
+ local_irq_save_hw(flags); \
+ (cpuid) = ipipe_processor_id(); \
+ } while(0)
+#define ipipe_unlock_cpu(flags) local_irq_restore_hw(flags)
+#define ipipe_get_cpu(flags) ipipe_lock_cpu(flags)
+#define ipipe_put_cpu(flags) ipipe_unlock_cpu(flags)
+#define ipipe_current_domain (ipipe_percpu_domain[ipipe_processor_id()])
+
+#else /* !CONFIG_SMP */
+
+#define IPIPE_NR_CPUS 1
+#define ipipe_declare_cpuid const int cpuid = 0
+#define ipipe_load_cpuid() do { } while(0)
+#define ipipe_lock_cpu(flags) local_irq_save_hw(flags)
+#define ipipe_unlock_cpu(flags) local_irq_restore_hw(flags)
+#define ipipe_get_cpu(flags) do { flags = 0; } while(0)
+#define ipipe_put_cpu(flags) do { } while(0)
+#define ipipe_current_domain (ipipe_percpu_domain[0])
+
+#endif /* CONFIG_SMP */
+
+#define ipipe_virtual_irq_p(irq) ((irq) >= IPIPE_VIRQ_BASE && \
+ (irq) < IPIPE_NR_IRQS)
+
+typedef void (*ipipe_irq_handler_t)(unsigned irq,
+ void *cookie);
+
+#define IPIPE_SAME_HANDLER ((ipipe_irq_handler_t)(-1))
+
+typedef int (*ipipe_irq_ackfn_t)(unsigned irq);
+
+typedef int (*ipipe_event_handler_t)(unsigned event,
+ struct ipipe_domain *from,
+ void *data);
+struct ipipe_domain {
+
+ struct list_head p_link; /* Link in pipeline */
+
+ struct ipcpudata {
+ unsigned long status;
+ unsigned long irq_pending_hi;
+ unsigned long irq_pending_lo[IPIPE_IRQ_IWORDS];
+ struct ipirqcnt {
+ unsigned long pending_hits;
+ unsigned long total_hits;
+ } irq_counters[IPIPE_NR_IRQS];
+ unsigned long long evsync;
+ } ____cacheline_aligned_in_smp cpudata[IPIPE_NR_CPUS];
+
+ struct {
+ unsigned long control;
+ ipipe_irq_ackfn_t acknowledge;
+ ipipe_irq_handler_t handler;
+ void *cookie;
+ } ____cacheline_aligned irqs[IPIPE_NR_IRQS];
+
+ ipipe_event_handler_t evhand[IPIPE_NR_EVENTS]; /* Event handlers. */
+ unsigned long long evself; /* Self-monitored event bits. */
+ unsigned long flags;
+ unsigned domid;
+ const char *name;
+ int priority;
+ void *pdd;
+};
+
+#define IPIPE_HEAD_PRIORITY (-1) /* For domains always heading the pipeline */
+
+struct ipipe_domain_attr {
+
+ unsigned domid; /* Domain identifier -- Magic value set by caller */
+ const char *name; /* Domain name -- Warning: won't be dup'ed! */
+ int priority; /* Priority in interrupt pipeline */
+ void (*entry) (void); /* Domain entry point */
+ void *pdd; /* Per-domain (opaque) data pointer */
+};
+
+/* The following macros must be used hw interrupts off. */
+
+#define __ipipe_irq_cookie(ipd,irq) (ipd)->irqs[irq].cookie
+#define __ipipe_irq_handler(ipd,irq) (ipd)->irqs[irq].handler
+
+#define __ipipe_cpudata_irq_hits(ipd,cpuid,irq) ((ipd)->cpudata[cpuid].irq_counters[irq].total_hits)
+
+#define __ipipe_set_irq_bit(ipd,cpuid,irq) \
+do { \
+ if (!test_bit(IPIPE_LOCK_FLAG,&(ipd)->irqs[irq].control)) { \
+ __set_bit(irq & IPIPE_IRQ_IMASK,&(ipd)->cpudata[cpuid].irq_pending_lo[irq >> IPIPE_IRQ_ISHIFT]); \
+ __set_bit(irq >> IPIPE_IRQ_ISHIFT,&(ipd)->cpudata[cpuid].irq_pending_hi); \
+ } \
+} while(0)
+
+#define __ipipe_clear_pend(ipd,cpuid,irq) \
+do { \
+ __clear_bit(irq & IPIPE_IRQ_IMASK,&(ipd)->cpudata[cpuid].irq_pending_lo[irq >> IPIPE_IRQ_ISHIFT]); \
+ if ((ipd)->cpudata[cpuid].irq_pending_lo[irq >> IPIPE_IRQ_ISHIFT] == 0) \
+ __clear_bit(irq >> IPIPE_IRQ_ISHIFT,&(ipd)->cpudata[cpuid].irq_pending_hi); \
+} while(0)
+
+#define __ipipe_lock_irq(ipd,cpuid,irq) \
+do { \
+ if (!test_and_set_bit(IPIPE_LOCK_FLAG,&(ipd)->irqs[irq].control)) \
+ __ipipe_clear_pend(ipd,cpuid,irq); \
+} while(0)
+
+#define __ipipe_unlock_irq(ipd,irq) \
+do { \
+ int __cpuid, __nr_cpus = num_online_cpus(); \
+ if (test_and_clear_bit(IPIPE_LOCK_FLAG,&(ipd)->irqs[irq].control)) \
+ for (__cpuid = 0; __cpuid < __nr_cpus; __cpuid++) \
+ if ((ipd)->cpudata[__cpuid].irq_counters[irq].pending_hits > 0) { /* We need atomic ops next. */ \
+ set_bit(irq & IPIPE_IRQ_IMASK,&(ipd)->cpudata[__cpuid].irq_pending_lo[irq >> IPIPE_IRQ_ISHIFT]); \
+ set_bit(irq >> IPIPE_IRQ_ISHIFT,&(ipd)->cpudata[__cpuid].irq_pending_hi); \
+ } \
+} while(0)
+
+#define __ipipe_clear_irq(ipd,irq) \
+do { \
+ int __cpuid, __nr_cpus = num_online_cpus(); \
+ clear_bit(IPIPE_LOCK_FLAG,&(ipd)->irqs[irq].control); \
+ for (__cpuid = 0; __cpuid < __nr_cpus; __cpuid++) { \
+ (ipd)->cpudata[__cpuid].irq_counters[irq].pending_hits = 0; \
+ __ipipe_clear_pend(ipd,__cpuid,irq); \
+ } \
+} while(0)
+
+#define spin_lock_hw(x) spin_lock(x)
+#define spin_unlock_hw(x) spin_unlock(x)
+#define spin_trylock_hw(x) spin_trylock(x)
+#define write_lock_hw(x) write_lock(x)
+#define write_unlock_hw(x) write_unlock(x)
+#define write_trylock_hw(x) write_trylock(x)
+#define read_lock_hw(x) read_lock(x)
+#define read_unlock_hw(x) read_unlock(x)
+
+typedef spinlock_t ipipe_spinlock_t;
+typedef rwlock_t ipipe_rwlock_t;
+#define IPIPE_SPIN_LOCK_UNLOCKED SPIN_LOCK_UNLOCKED
+#define IPIPE_RW_LOCK_UNLOCKED RW_LOCK_UNLOCKED
+
+#define spin_lock_irqsave_hw(x,flags) \
+do { \
+ local_irq_save_hw(flags); \
+ spin_lock_hw(x); \
+} while (0)
+
+#define spin_unlock_irqrestore_hw(x,flags) \
+do { \
+ spin_unlock_hw(x); \
+ local_irq_restore_hw(flags); \
+} while (0)
+
+#define spin_lock_irq_hw(x) \
+do { \
+ local_irq_disable_hw(); \
+ spin_lock_hw(x); \
+} while (0)
+
+#define spin_unlock_irq_hw(x) \
+do { \
+ spin_unlock_hw(x); \
+ local_irq_enable_hw(); \
+} while (0)
+
+#define read_lock_irqsave_hw(lock, flags) \
+do { \
+ local_irq_save_hw(flags); \
+ read_lock_hw(lock); \
+} while (0)
+
+#define read_unlock_irqrestore_hw(lock, flags) \
+do { \
+ read_unlock_hw(lock); \
+ local_irq_restore_hw(flags); \
+} while (0)
+
+#define write_lock_irqsave_hw(lock, flags) \
+do { \
+ local_irq_save_hw(flags); \
+ write_lock_hw(lock); \
+} while (0)
+
+#define write_unlock_irqrestore_hw(lock, flags) \
+do { \
+ write_unlock_hw(lock); \
+ local_irq_restore_hw(flags); \
+} while (0)
+
+extern struct ipipe_domain *ipipe_percpu_domain[];
+
+extern struct ipipe_domain ipipe_root;
+
+#define ipipe_root_domain (&ipipe_root)
+
+extern unsigned __ipipe_printk_virq;
+
+extern unsigned long __ipipe_virtual_irq_map;
+
+extern struct list_head __ipipe_pipeline;
+
+extern ipipe_spinlock_t __ipipe_pipelock;
+
+extern int __ipipe_event_monitors[];
+
+/* Private interface */
+
+void ipipe_init(void);
+
+#ifdef CONFIG_PROC_FS
+void ipipe_init_proc(void);
+#else /* !CONFIG_PROC_FS */
+#define ipipe_init_proc() do { } while(0)
+#endif /* CONFIG_PROC_FS */
+
+void __ipipe_init_stage(struct ipipe_domain *ipd);
+
+void __ipipe_cleanup_domain(struct ipipe_domain *ipd);
+
+void __ipipe_add_domain_proc(struct ipipe_domain *ipd);
+
+void __ipipe_remove_domain_proc(struct ipipe_domain *ipd);
+
+void __ipipe_flush_printk(unsigned irq, void *cookie);
+
+void __ipipe_stall_root(void);
+
+void __ipipe_unstall_root(void);
+
+unsigned long __ipipe_test_root(void);
+
+unsigned long __ipipe_test_and_stall_root(void);
+
+void FASTCALL(__ipipe_walk_pipeline(struct list_head *pos, int cpuid));
+
+void FASTCALL(__ipipe_restore_root(unsigned long flags));
+
+int FASTCALL(__ipipe_schedule_irq(unsigned irq, struct list_head *head));
+
+int FASTCALL(__ipipe_dispatch_event(unsigned event, void *data));
+
+int FASTCALL(__ipipe_dispatch_wired(struct ipipe_domain *head, unsigned irq));
+
+void FASTCALL(__ipipe_sync_stage(unsigned long syncmask));
+
+#ifndef __ipipe_sync_pipeline
+#define __ipipe_sync_pipeline(syncmask) __ipipe_sync_stage(syncmask)
+#endif
+
+#ifndef __ipipe_run_irqtail
+#define __ipipe_run_irqtail() do { } while(0)
+#endif
+
+#define __ipipe_pipeline_head_p(ipd) (&(ipd)->p_link == __ipipe_pipeline.next)
+
+/*
+ * Keep the following as a macro, so that client code could check for
+ * the support of the invariant pipeline head optimization.
+ */
+#define __ipipe_pipeline_head() list_entry(__ipipe_pipeline.next,struct ipipe_domain,p_link)
+
+#define __ipipe_event_monitored_p(ev) \
+ (__ipipe_event_monitors[ev] > 0 || (ipipe_current_domain->evself & (1LL << ev)))
+
+#ifdef CONFIG_SMP
+
+cpumask_t __ipipe_set_irq_affinity(unsigned irq,
+ cpumask_t cpumask);
+
+int FASTCALL(__ipipe_send_ipi(unsigned ipi,
+ cpumask_t cpumask));
+
+#endif /* CONFIG_SMP */
+
+/* Called with hw interrupts off. */
+static inline void __ipipe_switch_to(struct ipipe_domain *out,
+ struct ipipe_domain *in, int cpuid)
+{
+ void ipipe_suspend_domain(void);
+
+ /*
+ * "in" is guaranteed to be closer than "out" from the head of the
+ * pipeline (and obviously different).
+ */
+
+ out->cpudata[cpuid].evsync = 0;
+ ipipe_percpu_domain[cpuid] = in;
+
+ ipipe_suspend_domain(); /* Sync stage and propagate interrupts. */
+ ipipe_load_cpuid(); /* Processor might have changed. */
+
+ if (ipipe_percpu_domain[cpuid] == in)
+ /*
+ * Otherwise, something has changed the current domain under
+ * our feet recycling the register set; do not override.
+ */
+ ipipe_percpu_domain[cpuid] = out;
+}
+
+#define ipipe_sigwake_notify(p) \
+do { \
+ if (((p)->flags & PF_EVNOTIFY) && __ipipe_event_monitored_p(IPIPE_EVENT_SIGWAKE)) \
+ __ipipe_dispatch_event(IPIPE_EVENT_SIGWAKE,p); \
+} while(0)
+
+#define ipipe_exit_notify(p) \
+do { \
+ if (((p)->flags & PF_EVNOTIFY) && __ipipe_event_monitored_p(IPIPE_EVENT_EXIT)) \
+ __ipipe_dispatch_event(IPIPE_EVENT_EXIT,p); \
+} while(0)
+
+#define ipipe_setsched_notify(p) \
+do { \
+ if (((p)->flags & PF_EVNOTIFY) && __ipipe_event_monitored_p(IPIPE_EVENT_SETSCHED)) \
+ __ipipe_dispatch_event(IPIPE_EVENT_SETSCHED,p); \
+} while(0)
+
+#define ipipe_schedule_notify(prev, next) \
+do { \
+ if ((((prev)->flags|(next)->flags) & PF_EVNOTIFY) && \
+ __ipipe_event_monitored_p(IPIPE_EVENT_SCHEDULE)) \
+ __ipipe_dispatch_event(IPIPE_EVENT_SCHEDULE,next); \
+} while(0)
+
+#define ipipe_trap_notify(ex, regs) \
+({ \
+ ipipe_declare_cpuid; \
+ int ret = 0; \
+ ipipe_load_cpuid(); \
+ if ((test_bit(IPIPE_NOSTACK_FLAG, &ipipe_current_domain->cpudata[cpuid].status) || \
+ ((current)->flags & PF_EVNOTIFY)) && \
+ __ipipe_event_monitored_p(ex)) \
+ ret = __ipipe_dispatch_event(ex, regs); \
+ ret; \
+})
+
+static inline void ipipe_init_notify(struct task_struct *p)
+{
+ if (__ipipe_event_monitored_p(IPIPE_EVENT_INIT))
+ __ipipe_dispatch_event(IPIPE_EVENT_INIT,p);
+}
+
+struct mm_struct;
+
+static inline void ipipe_cleanup_notify(struct mm_struct *mm)
+{
+ if (__ipipe_event_monitored_p(IPIPE_EVENT_CLEANUP))
+ __ipipe_dispatch_event(IPIPE_EVENT_CLEANUP,mm);
+}
+
+/* Public interface */
+
+int ipipe_register_domain(struct ipipe_domain *ipd,
+ struct ipipe_domain_attr *attr);
+
+int ipipe_unregister_domain(struct ipipe_domain *ipd);
+
+void ipipe_suspend_domain(void);
+
+int ipipe_virtualize_irq(struct ipipe_domain *ipd,
+ unsigned irq,
+ ipipe_irq_handler_t handler,
+ void *cookie,
+ ipipe_irq_ackfn_t acknowledge,
+ unsigned modemask);
+
+static inline int ipipe_share_irq(unsigned irq,
+ ipipe_irq_ackfn_t acknowledge)
+{
+ return ipipe_virtualize_irq(ipipe_current_domain,
+ irq,
+ IPIPE_SAME_HANDLER,
+ NULL,
+ acknowledge,
+ IPIPE_SHARED_MASK | IPIPE_HANDLE_MASK |
+ IPIPE_PASS_MASK);
+}
+
+int ipipe_control_irq(unsigned irq,
+ unsigned clrmask,
+ unsigned setmask);
+
+unsigned ipipe_alloc_virq(void);
+
+int ipipe_free_virq(unsigned virq);
+
+int FASTCALL(ipipe_trigger_irq(unsigned irq));
+
+static inline int ipipe_propagate_irq(unsigned irq)
+{
+ return __ipipe_schedule_irq(irq, ipipe_current_domain->p_link.next);
+}
+
+static inline int ipipe_schedule_irq(unsigned irq)
+{
+
+ return __ipipe_schedule_irq(irq, &ipipe_current_domain->p_link);
+}
+
+void FASTCALL(ipipe_stall_pipeline_from(struct ipipe_domain *ipd));
+
+unsigned long FASTCALL(ipipe_test_and_stall_pipeline_from(struct ipipe_domain *ipd));
+
+void FASTCALL(ipipe_unstall_pipeline_from(struct ipipe_domain *ipd));
+
+unsigned long FASTCALL(ipipe_test_and_unstall_pipeline_from(struct ipipe_domain *ipd));
+
+void FASTCALL(ipipe_restore_pipeline_from(struct ipipe_domain *ipd,
+ unsigned long x));
+
+static inline unsigned long ipipe_test_pipeline_from(struct ipipe_domain *ipd)
+{
+ unsigned long flags, x;
+ ipipe_declare_cpuid;
+
+ ipipe_get_cpu(flags);
+ x = test_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+ ipipe_put_cpu(flags);
+
+ return x;
+}
+
+static inline void ipipe_restore_pipeline_nosync(struct ipipe_domain *ipd,
+ unsigned long x, int cpuid)
+{
+ /*
+ * If cpuid is current, then it must be held on entry
+ * (ipipe_get_cpu/local_irq_save_hw/local_irq_disable_hw).
+ */
+
+ if (x)
+ __set_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+ else
+ __clear_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+}
+
+static inline void ipipe_stall_pipeline_head(void)
+{
+ ipipe_declare_cpuid;
+ unsigned long flags;
+
+ ipipe_lock_cpu(flags);
+ __set_bit(IPIPE_STALL_FLAG, &__ipipe_pipeline_head()->cpudata[cpuid].status);
+}
+
+static inline unsigned long ipipe_test_and_stall_pipeline_head(void)
+{
+ unsigned long flags;
+ ipipe_declare_cpuid;
+
+ ipipe_lock_cpu(flags);
+ return __test_and_set_bit(IPIPE_STALL_FLAG, &__ipipe_pipeline_head()->cpudata[cpuid].status);
+}
+
+void ipipe_unstall_pipeline_head(void);
+
+void FASTCALL(__ipipe_restore_pipeline_head(struct ipipe_domain *head,
+ unsigned long x));
+
+static inline void ipipe_restore_pipeline_head(unsigned long x)
+{
+ struct ipipe_domain *head = __ipipe_pipeline_head();
+ /* On some archs, __test_and_set_bit() might return different
+ * truth value than test_bit(), so we test the exclusive OR of
+ * both statuses, assuming that the lowest bit is always set in
+ * the truth value (if this is wrong, the failed optimization will
+ * be caught in __ipipe_restore_pipeline_head() if
+ * CONFIG_DEBUG_KERNEL is set). */
+ if ((x ^ test_bit(IPIPE_STALL_FLAG, &head->cpudata[ipipe_processor_id()].status)) & 1)
+ __ipipe_restore_pipeline_head(head,x);
+}
+
+#define ipipe_unstall_pipeline() \
+ ipipe_unstall_pipeline_from(ipipe_current_domain)
+
+#define ipipe_test_and_unstall_pipeline() \
+ ipipe_test_and_unstall_pipeline_from(ipipe_current_domain)
+
+#define ipipe_test_pipeline() \
+ ipipe_test_pipeline_from(ipipe_current_domain)
+
+#define ipipe_test_and_stall_pipeline() \
+ ipipe_test_and_stall_pipeline_from(ipipe_current_domain)
+
+#define ipipe_stall_pipeline() \
+ ipipe_stall_pipeline_from(ipipe_current_domain)
+
+#define ipipe_restore_pipeline(x) \
+ ipipe_restore_pipeline_from(ipipe_current_domain, (x))
+
+void ipipe_init_attr(struct ipipe_domain_attr *attr);
+
+int ipipe_get_sysinfo(struct ipipe_sysinfo *sysinfo);
+
+int ipipe_tune_timer(unsigned long ns,
+ int flags);
+
+unsigned long ipipe_critical_enter(void (*syncfn) (void));
+
+void ipipe_critical_exit(unsigned long flags);
+
+static inline void ipipe_set_printk_sync(struct ipipe_domain *ipd)
+{
+ set_bit(IPIPE_SPRINTK_FLAG, &ipd->flags);
+}
+
+static inline void ipipe_set_printk_async(struct ipipe_domain *ipd)
+{
+ clear_bit(IPIPE_SPRINTK_FLAG, &ipd->flags);
+}
+
+static inline void ipipe_set_foreign_stack(struct ipipe_domain *ipd)
+{
+ /* Must be called hw interrupts off. */
+ ipipe_declare_cpuid; ipipe_load_cpuid();
+ __set_bit(IPIPE_NOSTACK_FLAG, &ipd->cpudata[cpuid].status);
+}
+
+static inline void ipipe_clear_foreign_stack(struct ipipe_domain *ipd)
+{
+ /* Must be called hw interrupts off. */
+ ipipe_declare_cpuid; ipipe_load_cpuid();
+ __clear_bit(IPIPE_NOSTACK_FLAG, &ipd->cpudata[cpuid].status);
+}
+
+#define ipipe_safe_current() \
+({ \
+ ipipe_declare_cpuid; \
+ struct task_struct *p; \
+ ipipe_load_cpuid(); \
+ p = test_bit(IPIPE_NOSTACK_FLAG, \
+ &ipipe_percpu_domain[cpuid]->cpudata[cpuid].status) ? &init_task : current; \
+ p; \
+})
+
+ipipe_event_handler_t ipipe_catch_event(struct ipipe_domain *ipd,
+ unsigned event,
+ ipipe_event_handler_t handler);
+
+cpumask_t ipipe_set_irq_affinity(unsigned irq,
+ cpumask_t cpumask);
+
+int FASTCALL(ipipe_send_ipi(unsigned ipi,
+ cpumask_t cpumask));
+
+int ipipe_setscheduler_root(struct task_struct *p,
+ int policy,
+ int prio);
+
+int ipipe_reenter_root(struct task_struct *prev,
+ int policy,
+ int prio);
+
+int ipipe_alloc_ptdkey(void);
+
+int ipipe_free_ptdkey(int key);
+
+int FASTCALL(ipipe_set_ptd(int key,
+ void *value));
+
+void *FASTCALL(ipipe_get_ptd(int key));
+
+#define local_irq_enable_hw_cond() local_irq_enable_hw()
+#define local_irq_disable_hw_cond() local_irq_disable_hw()
+#define local_irq_save_hw_cond(flags) local_irq_save_hw(flags)
+#define local_irq_restore_hw_cond(flags) local_irq_restore_hw(flags)
+
+#define local_irq_enable_nohead(ipd) \
+ do { \
+ if (!__ipipe_pipeline_head_p(ipd)) \
+ local_irq_enable_hw(); \
+ } while(0)
+
+#define local_irq_disable_nohead(ipd) \
+ do { \
+ if (!__ipipe_pipeline_head_p(ipd)) \
+ local_irq_disable_hw(); \
+ } while(0)
+
+#define spin_lock_irqsave_hw_cond(lock,flags) spin_lock_irqsave_hw(lock,flags)
+#define spin_unlock_irqrestore_hw_cond(lock,flags) spin_unlock_irqrestore_hw(lock,flags)
+#define spin_lock_hw_cond(lock) spin_lock_hw(lock)
+#define spin_unlock_hw_cond(lock) spin_unlock_hw(lock)
+
+#define ipipe_irq_lock(irq) \
+ do { \
+ ipipe_declare_cpuid; \
+ ipipe_load_cpuid(); \
+ __ipipe_lock_irq(ipipe_percpu_domain[cpuid], cpuid, irq);\
+ } while(0)
+
+#define ipipe_irq_unlock(irq) \
+ do { \
+ ipipe_declare_cpuid; \
+ ipipe_load_cpuid(); \
+ __ipipe_unlock_irq(ipipe_percpu_domain[cpuid], irq); \
+ } while(0)
+
+#define ipipe_root_domain_p (ipipe_current_domain == ipipe_root_domain)
+
+#else /* !CONFIG_IPIPE */
+
+#define ipipe_root_domain_p 1
+
+#define ipipe_init() do { } while(0)
+#define ipipe_suspend_domain() do { } while(0)
+#define ipipe_sigwake_notify(p) do { } while(0)
+#define ipipe_setsched_notify(p) do { } while(0)
+#define ipipe_init_notify(p) do { } while(0)
+#define ipipe_exit_notify(p) do { } while(0)
+#define ipipe_trap_notify(t,r) 0
+#define ipipe_cleanup_notify(mm) do { } while(0)
+#define ipipe_init_proc() do { } while(0)
+
+#define spin_lock_hw(lock) spin_lock(lock)
+#define spin_unlock_hw(lock) spin_unlock(lock)
+#define spin_lock_irq_hw(lock) spin_lock_irq(lock)
+#define spin_unlock_irq_hw(lock) spin_unlock_irq(lock)
+#define spin_lock_irqsave_hw(lock,flags) spin_lock_irqsave(lock, flags)
+#define spin_unlock_irqrestore_hw(lock,flags) spin_unlock_irqrestore(lock, flags)
+
+#define local_irq_enable_hw_cond() do { } while(0)
+#define local_irq_disable_hw_cond() do { } while(0)
+#define local_irq_save_hw_cond(flags) do { (void)(flags); } while(0)
+#define local_irq_restore_hw_cond(flags) do { } while(0)
+#define spin_lock_irqsave_hw_cond(lock,flags) do { (void)(flags); spin_lock(lock); } while(0)
+#define spin_unlock_irqrestore_hw_cond(lock,flags) spin_unlock(lock)
+#define spin_lock_hw_cond(lock) do { } while(0)
+#define spin_unlock_hw_cond(lock) do { } while(0)
+
+#define ipipe_irq_lock(irq) do { } while(0)
+#define ipipe_irq_unlock(irq) do { } while(0)
+
+#endif /* CONFIG_IPIPE */
+
+#endif /* !__LINUX_IPIPE_H */
diff -uNrp 2.4.35.5/include/linux/sched.h 2.4.35.5-i386-ipipe/include/linux/sched.h
--- 2.4.35.5/include/linux/sched.h 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/include/linux/sched.h 2007-12-22 16:48:48.000000000 +0100
@@ -6,6 +6,7 @@
extern unsigned long event;
#include <linux/config.h>
+#include <linux/ipipe.h>
#include <linux/binfmts.h>
#include <linux/threads.h>
#include <linux/kernel.h>
@@ -91,6 +92,11 @@ extern int last_pid;
#define TASK_UNINTERRUPTIBLE 2
#define TASK_ZOMBIE 4
#define TASK_STOPPED 8
+#ifdef CONFIG_IPIPE
+#define TASK_NOWAKEUP 1024
+#else /* !CONFIG_IPIPE */
+#define TASK_NOWAKEUP 0
+#endif /* CONFIG_IPIPE */
#define __set_task_state(tsk, state_value) \
do { (tsk)->state = (state_value); } while (0)
@@ -415,6 +421,10 @@ struct task_struct {
/* journalling filesystem info */
void *journal_info;
+
+#ifdef CONFIG_IPIPE
+ void *ptd[IPIPE_ROOT_NPTDKEYS];
+#endif
};
/*
@@ -435,6 +445,11 @@ struct task_struct {
#define PF_FSTRANS 0x00008000 /* inside a filesystem transaction */
#define PF_USEDFPU 0x00100000 /* task used FPU this quantum (SMP) */
+#ifdef CONFIG_IPIPE
+#define PF_EVNOTIFY 0x40000000 /* Notify other domains about internal events */
+#else
+#define PF_EVNOTIFY 0
+#endif /* CONFIG_IPIPE */
/*
* Ptrace flags
diff -uNrp 2.4.35.5/init/main.c 2.4.35.5-i386-ipipe/init/main.c
--- 2.4.35.5/init/main.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/init/main.c 2007-12-22 16:46:39.000000000 +0100
@@ -373,7 +373,10 @@ asmlinkage void __init start_kernel(void
sched_init();
softirq_init();
time_init();
-
+ /* We need to wait for the interrupt and time subsystems to be
+ initialized before enabling the pipeline. */
+ ipipe_init();
+
/*
* HACK ALERT! This is early. We're enabling the console before
* we've done PCI setups etc, and console_init() must be aware of
@@ -494,6 +497,7 @@ static void __init do_basic_setup(void)
#ifdef CONFIG_SYSCTL
sysctl_init();
#endif
+ ipipe_init_proc();
/*
* Ok, at this point all CPU's should be initialized, so
diff -uNrp 2.4.35.5/kernel/Makefile 2.4.35.5-i386-ipipe/kernel/Makefile
--- 2.4.35.5/kernel/Makefile 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/Makefile 2007-12-22 16:46:39.000000000 +0100
@@ -16,6 +16,7 @@ obj-y = sched.o dma.o fork.o exec_do
sysctl.o acct.o capability.o ptrace.o timer.o user.o \
signal.o sys.o kmod.o context.o
+obj-$(CONFIG_IPIPE) += ipipe/ipipe.o
obj-$(CONFIG_UID16) += uid16.o
obj-$(CONFIG_MODULES) += ksyms.o
obj-$(CONFIG_PM) += pm.o
@@ -29,4 +30,6 @@ ifneq ($(CONFIG_IA64),y)
CFLAGS_sched.o := $(PROFILING) -fno-omit-frame-pointer
endif
+subdir-$(CONFIG_IPIPE) += ipipe
+
include $(TOPDIR)/Rules.make
diff -uNrp 2.4.35.5/kernel/exit.c 2.4.35.5-i386-ipipe/kernel/exit.c
--- 2.4.35.5/kernel/exit.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/exit.c 2007-12-22 16:46:39.000000000 +0100
@@ -439,6 +439,7 @@ fake_volatile:
#ifdef CONFIG_BSD_PROCESS_ACCT
acct_process(code);
#endif
+ ipipe_exit_notify(tsk);
__exit_mm(tsk);
lock_kernel();
diff -uNrp 2.4.35.5/kernel/fork.c 2.4.35.5-i386-ipipe/kernel/fork.c
--- 2.4.35.5/kernel/fork.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/fork.c 2007-12-22 16:46:39.000000000 +0100
@@ -286,6 +286,7 @@ void mmput(struct mm_struct *mm)
mmlist_nr--;
spin_unlock(&mmlist_lock);
exit_mmap(mm);
+ ipipe_cleanup_notify(mm);
mmdrop(mm);
}
}
@@ -603,7 +604,7 @@ static inline void copy_flags(unsigned l
{
unsigned long new_flags = p->flags;
- new_flags &= ~(PF_SUPERPRIV | PF_USEDFPU);
+ new_flags &= ~(PF_SUPERPRIV | PF_USEDFPU | PF_EVNOTIFY);
new_flags |= PF_FORKNOEXEC;
if (!(clone_flags & CLONE_PTRACE))
p->ptrace = 0;
@@ -823,6 +824,14 @@ int do_fork(unsigned long clone_flags, u
if (p->ptrace & PT_PTRACED)
send_sig(SIGSTOP, p, 1);
+#ifdef CONFIG_IPIPE
+ {
+ int k;
+
+ for (k = 0; k < IPIPE_ROOT_NPTDKEYS; k++)
+ p->ptd[k] = NULL;
+ }
+#endif /* CONFIG_IPIPE */
wake_up_process(p); /* do this last */
++total_forks;
if (clone_flags & CLONE_VFORK)
diff -uNrp 2.4.35.5/kernel/ipipe/Makefile 2.4.35.5-i386-ipipe/kernel/ipipe/Makefile
--- 2.4.35.5/kernel/ipipe/Makefile 1970-01-01 01:00:00.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/ipipe/Makefile 2007-12-22 16:46:39.000000000 +0100
@@ -0,0 +1,7 @@
+O_TARGET := ipipe.o
+
+obj-y := core.o generic.o
+
+export-objs := $(obj-y)
+
+include $(TOPDIR)/Rules.make
diff -uNrp 2.4.35.5/kernel/ipipe/core.c 2.4.35.5-i386-ipipe/kernel/ipipe/core.c
--- 2.4.35.5/kernel/ipipe/core.c 1970-01-01 01:00:00.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/ipipe/core.c 2007-12-22 16:46:39.000000000 +0100
@@ -0,0 +1,1055 @@
+/* -*- linux-c -*-
+ * linux/kernel/ipipe/core.c
+ *
+ * Copyright (C) 2002-2005 Philippe Gerum.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Architecture-independent I-PIPE core support.
+ */
+
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <linux/bitops.h>
+#include <linux/ipipe.h>
+#include <linux/interrupt.h>
+#ifdef CONFIG_PROC_FS
+#include <linux/proc_fs.h>
+#endif /* CONFIG_PROC_FS */
+
+struct ipipe_domain ipipe_root =
+ { .cpudata = {[0 ... IPIPE_NR_CPUS-1] =
+ { .status = (1<<IPIPE_STALL_FLAG) } } };
+
+struct ipipe_domain *ipipe_percpu_domain[IPIPE_NR_CPUS] =
+ {[0 ... IPIPE_NR_CPUS - 1] = &ipipe_root };
+
+ipipe_spinlock_t __ipipe_pipelock = IPIPE_SPIN_LOCK_UNLOCKED;
+
+struct list_head __ipipe_pipeline;
+
+unsigned long __ipipe_virtual_irq_map = 0;
+
+unsigned __ipipe_printk_virq;
+
+int __ipipe_event_monitors[IPIPE_NR_EVENTS];
+
+/*
+ * ipipe_init() -- Initialization routine of the IPIPE layer. Called
+ * by the host kernel early during the boot procedure.
+ */
+void ipipe_init(void)
+{
+ struct ipipe_domain *ipd = &ipipe_root;
+
+ __ipipe_check_platform(); /* Do platform dependent checks first. */
+
+ /*
+ * A lightweight registration code for the root domain. We are
+ * running on the boot CPU, hw interrupts are off, and
+ * secondary CPUs are still lost in space.
+ */
+
+ INIT_LIST_HEAD(&__ipipe_pipeline);
+
+ ipd->name = "Linux";
+ ipd->domid = IPIPE_ROOT_ID;
+ ipd->priority = IPIPE_ROOT_PRIO;
+
+ __ipipe_init_stage(ipd);
+
+ INIT_LIST_HEAD(&ipd->p_link);
+ list_add_tail(&ipd->p_link, &__ipipe_pipeline);
+
+ __ipipe_init_platform();
+
+ __ipipe_printk_virq = ipipe_alloc_virq(); /* Cannot fail here. */
+ ipd->irqs[__ipipe_printk_virq].handler = &__ipipe_flush_printk;
+ ipd->irqs[__ipipe_printk_virq].cookie = NULL;
+ ipd->irqs[__ipipe_printk_virq].acknowledge = NULL;
+ ipd->irqs[__ipipe_printk_virq].control = IPIPE_HANDLE_MASK;
+
+ __ipipe_enable_pipeline();
+
+ printk(KERN_INFO "I-pipe %s: pipeline enabled.\n",
+ IPIPE_VERSION_STRING);
+}
+
+void __ipipe_init_stage(struct ipipe_domain *ipd)
+{
+ int cpuid, n;
+
+ for (cpuid = 0; cpuid < IPIPE_NR_CPUS; cpuid++) {
+ ipd->cpudata[cpuid].irq_pending_hi = 0;
+
+ for (n = 0; n < IPIPE_IRQ_IWORDS; n++)
+ ipd->cpudata[cpuid].irq_pending_lo[n] = 0;
+
+ for (n = 0; n < IPIPE_NR_IRQS; n++) {
+ ipd->cpudata[cpuid].irq_counters[n].pending_hits = 0;
+ ipd->cpudata[cpuid].irq_counters[n].total_hits = 0;
+ }
+ ipd->cpudata[cpuid].evsync = 0;
+ }
+
+ for (n = 0; n < IPIPE_NR_IRQS; n++) {
+ ipd->irqs[n].acknowledge = NULL;
+ ipd->irqs[n].handler = NULL;
+ ipd->irqs[n].control = IPIPE_PASS_MASK; /* Pass but don't handle */
+ }
+
+ for (n = 0; n < IPIPE_NR_EVENTS; n++)
+ ipd->evhand[n] = NULL;
+
+ ipd->evself = 0;
+
+#ifdef CONFIG_SMP
+ ipd->irqs[IPIPE_CRITICAL_IPI].acknowledge = &__ipipe_ack_system_irq;
+ ipd->irqs[IPIPE_CRITICAL_IPI].handler = &__ipipe_do_critical_sync;
+ ipd->irqs[IPIPE_CRITICAL_IPI].cookie = NULL;
+ /* Immediately handle in the current domain but *never* pass */
+ ipd->irqs[IPIPE_CRITICAL_IPI].control =
+ IPIPE_HANDLE_MASK|IPIPE_STICKY_MASK|IPIPE_SYSTEM_MASK;
+#endif /* CONFIG_SMP */
+}
+
+void __ipipe_cleanup_domain(struct ipipe_domain *ipd)
+{
+ ipipe_unstall_pipeline_from(ipd);
+
+#ifdef CONFIG_SMP
+ {
+ int cpu;
+
+ for_each_online_cpu(cpu) {
+ while (ipd->cpudata[cpu].irq_pending_hi != 0)
+ cpu_relax();
+ }
+ }
+#endif /* CONFIG_SMP */
+}
+
+void __ipipe_stall_root(void)
+{
+ ipipe_declare_cpuid;
+ unsigned long flags;
+
+ ipipe_get_cpu(flags); /* Care for migration. */
+ set_bit(IPIPE_STALL_FLAG, &ipipe_root_domain->cpudata[cpuid].status);
+ ipipe_put_cpu(flags);
+}
+
+void __ipipe_unstall_root(void)
+{
+ ipipe_declare_cpuid;
+
+ local_irq_disable_hw();
+
+ ipipe_load_cpuid();
+
+ __clear_bit(IPIPE_STALL_FLAG, &ipipe_root_domain->cpudata[cpuid].status);
+
+ if (unlikely(ipipe_root_domain->cpudata[cpuid].irq_pending_hi != 0))
+ __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
+
+ local_irq_enable_hw();
+}
+
+unsigned long __ipipe_test_root(void)
+{
+ unsigned long flags, x;
+ ipipe_declare_cpuid;
+
+ ipipe_get_cpu(flags); /* Care for migration. */
+ x = test_bit(IPIPE_STALL_FLAG, &ipipe_root_domain->cpudata[cpuid].status);
+ ipipe_put_cpu(flags);
+
+ return x;
+}
+
+unsigned long __ipipe_test_and_stall_root(void)
+{
+ unsigned long flags, x;
+ ipipe_declare_cpuid;
+
+ ipipe_get_cpu(flags); /* Care for migration. */
+ x = test_and_set_bit(IPIPE_STALL_FLAG,
+ &ipipe_root_domain->cpudata[cpuid].status);
+ ipipe_put_cpu(flags);
+
+ return x;
+}
+
+void fastcall __ipipe_restore_root(unsigned long x)
+{
+ if (x)
+ __ipipe_stall_root();
+ else
+ __ipipe_unstall_root();
+}
+
+void fastcall ipipe_stall_pipeline_from(struct ipipe_domain *ipd)
+{
+ ipipe_declare_cpuid;
+#ifdef CONFIG_SMP
+ unsigned long flags;
+
+ ipipe_lock_cpu(flags); /* Care for migration. */
+
+ __set_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+
+ if (!__ipipe_pipeline_head_p(ipd))
+ ipipe_unlock_cpu(flags);
+#else /* CONFIG_SMP */
+ set_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+
+ if (__ipipe_pipeline_head_p(ipd))
+ local_irq_disable_hw();
+#endif /* CONFIG_SMP */
+}
+
+unsigned long fastcall ipipe_test_and_stall_pipeline_from(struct ipipe_domain *ipd)
+{
+ ipipe_declare_cpuid;
+ unsigned long s;
+#ifdef CONFIG_SMP
+ unsigned long flags;
+
+ ipipe_lock_cpu(flags); /* Care for migration. */
+
+ s = __test_and_set_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+
+ if (!__ipipe_pipeline_head_p(ipd))
+ ipipe_unlock_cpu(flags);
+#else /* CONFIG_SMP */
+ s = test_and_set_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+
+ if (__ipipe_pipeline_head_p(ipd))
+ local_irq_disable_hw();
+#endif /* CONFIG_SMP */
+
+ return s;
+}
+
+/*
+ * ipipe_unstall_pipeline_from() -- Unstall the pipeline and
+ * synchronize pending interrupts for a given domain. See
+ * __ipipe_walk_pipeline() for more information.
+ */
+void fastcall ipipe_unstall_pipeline_from(struct ipipe_domain *ipd)
+{
+ struct list_head *pos;
+ unsigned long flags;
+ ipipe_declare_cpuid;
+
+ ipipe_lock_cpu(flags);
+
+ __clear_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+
+ if (ipd == ipipe_percpu_domain[cpuid])
+ pos = &ipd->p_link;
+ else
+ pos = __ipipe_pipeline.next;
+
+ __ipipe_walk_pipeline(pos, cpuid);
+
+ if (__ipipe_pipeline_head_p(ipd))
+ local_irq_enable_hw();
+ else
+ ipipe_unlock_cpu(flags);
+}
+
+unsigned long fastcall ipipe_test_and_unstall_pipeline_from(struct ipipe_domain *ipd)
+{
+ unsigned long flags, x;
+ ipipe_declare_cpuid;
+
+ ipipe_get_cpu(flags);
+ x = test_bit(IPIPE_STALL_FLAG, &ipd->cpudata[cpuid].status);
+ ipipe_unstall_pipeline_from(ipd);
+ ipipe_put_cpu(flags);
+
+ return x;
+}
+
+void fastcall ipipe_restore_pipeline_from(struct ipipe_domain *ipd,
+ unsigned long x)
+{
+ if (x)
+ ipipe_stall_pipeline_from(ipd);
+ else
+ ipipe_unstall_pipeline_from(ipd);
+}
+
+void ipipe_unstall_pipeline_head(void)
+{
+ struct ipipe_domain *head;
+ unsigned long flags;
+ ipipe_declare_cpuid;
+
+ ipipe_lock_cpu(flags);
+ head = __ipipe_pipeline_head();
+ __clear_bit(IPIPE_STALL_FLAG, &head->cpudata[cpuid].status);
+
+ if (unlikely(head->cpudata[cpuid].irq_pending_hi != 0)) {
+ if (likely(head == ipipe_percpu_domain[cpuid]))
+ __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
+ else
+ __ipipe_walk_pipeline(&head->p_link, cpuid);
+ }
+
+ local_irq_enable_hw();
+}
+
+void fastcall __ipipe_restore_pipeline_head(struct ipipe_domain *head, unsigned long x)
+{
+ ipipe_declare_cpuid;
+ unsigned long flags;
+
+ ipipe_get_cpu(flags);
+
+ if (x) {
+#ifdef CONFIG_DEBUG_KERNEL
+ static int warned;
+ if (!warned && test_and_set_bit(IPIPE_STALL_FLAG, &head->cpudata[cpuid].status)) {
+ /*
+ * Already stalled albeit ipipe_restore_pipeline_head()
+ * should have detected it? Send a warning once.\n");
+ */
+ warned = 1;
+ printk(KERN_WARNING
+ "I-pipe: ipipe_restore_pipeline_head() optimization failed.\n");
+ dump_stack();
+ }
+#else /* !CONFIG_DEBUG_KERNEL */
+ set_bit(IPIPE_STALL_FLAG, &head->cpudata[cpuid].status);
+#endif /* CONFIG_DEBUG_KERNEL */
+ }
+ else {
+ /* Hw interrupts must be off already. */
+ __clear_bit(IPIPE_STALL_FLAG, &head->cpudata[cpuid].status);
+ if (unlikely(head->cpudata[cpuid].irq_pending_hi != 0)) {
+ if (likely(head == ipipe_percpu_domain[cpuid]))
+ __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
+ else
+ __ipipe_walk_pipeline(&head->p_link, cpuid);
+ }
+ local_irq_enable_hw();
+ }
+}
+
+/* __ipipe_walk_pipeline(): Plays interrupts pending in the log. Must
+ be called with local hw interrupts disabled. */
+
+void fastcall __ipipe_walk_pipeline(struct list_head *pos, int cpuid)
+{
+ struct ipipe_domain *this_domain = ipipe_percpu_domain[cpuid];
+
+ while (pos != &__ipipe_pipeline) {
+ struct ipipe_domain *next_domain =
+ list_entry(pos, struct ipipe_domain, p_link);
+
+ if (test_bit
+ (IPIPE_STALL_FLAG, &next_domain->cpudata[cpuid].status))
+ break; /* Stalled stage -- do not go further. */
+
+ if (next_domain->cpudata[cpuid].irq_pending_hi != 0) {
+
+ if (next_domain == this_domain)
+ __ipipe_sync_stage(IPIPE_IRQMASK_ANY);
+ else {
+ __ipipe_switch_to(this_domain, next_domain,
+ cpuid);
+
+ ipipe_load_cpuid(); /* Processor might have changed. */
+
+ if (this_domain->cpudata[cpuid].
+ irq_pending_hi != 0
+ && !test_bit(IPIPE_STALL_FLAG,
+ &this_domain->cpudata[cpuid].status))
+ __ipipe_sync_stage(IPIPE_IRQMASK_ANY);
+ }
+
+ break;
+ } else if (next_domain == this_domain)
+ break;
+
+ pos = next_domain->p_link.next;
+ }
+}
+
+/*
+ * ipipe_suspend_domain() -- Suspend the current domain, switching to
+ * the next one which has pending work down the pipeline.
+ */
+void ipipe_suspend_domain(void)
+{
+ struct ipipe_domain *this_domain, *next_domain;
+ struct list_head *ln;
+ unsigned long flags;
+ ipipe_declare_cpuid;
+
+ ipipe_lock_cpu(flags);
+
+ this_domain = next_domain = ipipe_percpu_domain[cpuid];
+
+ __clear_bit(IPIPE_STALL_FLAG, &this_domain->cpudata[cpuid].status);
+
+ if (this_domain->cpudata[cpuid].irq_pending_hi != 0)
+ goto sync_stage;
+
+ for (;;) {
+ ln = next_domain->p_link.next;
+
+ if (ln == &__ipipe_pipeline)
+ break;
+
+ next_domain = list_entry(ln, struct ipipe_domain, p_link);
+
+ if (test_bit(IPIPE_STALL_FLAG,
+ &next_domain->cpudata[cpuid].status))
+ break;
+
+ if (next_domain->cpudata[cpuid].irq_pending_hi == 0)
+ continue;
+
+ ipipe_percpu_domain[cpuid] = next_domain;
+
+sync_stage:
+
+ __ipipe_sync_stage(IPIPE_IRQMASK_ANY);
+
+ ipipe_load_cpuid(); /* Processor might have changed. */
+
+ if (ipipe_percpu_domain[cpuid] != next_domain)
+ /*
+ * Something has changed the current domain under our
+ * feet, recycling the register set; take note.
+ */
+ this_domain = ipipe_percpu_domain[cpuid];
+ }
+
+ ipipe_percpu_domain[cpuid] = this_domain;
+
+ ipipe_unlock_cpu(flags);
+}
+
+/* ipipe_alloc_virq() -- Allocate a pipelined virtual/soft interrupt.
+ * Virtual interrupts are handled in exactly the same way than their
+ * hw-generated counterparts wrt pipelining.
+ */
+unsigned ipipe_alloc_virq(void)
+{
+ unsigned long flags, irq = 0;
+ int ipos;
+
+ spin_lock_irqsave_hw(&__ipipe_pipelock, flags);
+
+ if (__ipipe_virtual_irq_map != ~0) {
+ ipos = ffz(__ipipe_virtual_irq_map);
+ set_bit(ipos, &__ipipe_virtual_irq_map);
+ irq = ipos + IPIPE_VIRQ_BASE;
+ }
+
+ spin_unlock_irqrestore_hw(&__ipipe_pipelock, flags);
+
+ return irq;
+}
+
+/*
+ * ipipe_virtualize_irq() -- Attach a handler (and optionally a hw
+ * acknowledge routine) to an interrupt for the given domain.
+ */
+
+int ipipe_virtualize_irq(struct ipipe_domain *ipd,
+ unsigned irq,
+ ipipe_irq_handler_t handler,
+ void *cookie,
+ ipipe_irq_ackfn_t acknowledge,
+ unsigned modemask)
+{
+ unsigned long flags;
+ int err;
+
+ if (irq >= IPIPE_NR_IRQS)
+ return -EINVAL;
+
+ if (ipd->irqs[irq].control & IPIPE_SYSTEM_MASK)
+ return -EPERM;
+
+ if (!test_bit(IPIPE_AHEAD_FLAG, &ipd->flags))
+ /* Silently unwire interrupts for non-heading domains. */
+ modemask &= ~IPIPE_WIRED_MASK;
+
+ spin_lock_irqsave_hw(&__ipipe_pipelock, flags);
+
+ if (handler != NULL) {
+
+ if (handler == IPIPE_SAME_HANDLER) {
+ handler = ipd->irqs[irq].handler;
+ cookie = ipd->irqs[irq].cookie;
+
+ if (handler == NULL) {
+ err = -EINVAL;
+ goto unlock_and_exit;
+ }
+ } else if ((modemask & IPIPE_EXCLUSIVE_MASK) != 0 &&
+ ipd->irqs[irq].handler != NULL) {
+ err = -EBUSY;
+ goto unlock_and_exit;
+ }
+
+ if ((modemask & (IPIPE_SHARED_MASK | IPIPE_PASS_MASK)) ==
+ IPIPE_SHARED_MASK) {
+ err = -EINVAL;
+ goto unlock_and_exit;
+ }
+
+ /* Wired interrupts can only be delivered to domains
+ * always heading the pipeline. */
+
+ if ((modemask & IPIPE_WIRED_MASK) != 0) {
+ if ((modemask & (IPIPE_SHARED_MASK | IPIPE_PASS_MASK | IPIPE_STICKY_MASK)) != 0) {
+ err = -EINVAL;
+ goto unlock_and_exit;
+ }
+ modemask |= (IPIPE_HANDLE_MASK);
+ }
+
+ if ((modemask & IPIPE_STICKY_MASK) != 0)
+ modemask |= IPIPE_HANDLE_MASK;
+ } else
+ modemask &=
+ ~(IPIPE_HANDLE_MASK | IPIPE_STICKY_MASK |
+ IPIPE_SHARED_MASK | IPIPE_EXCLUSIVE_MASK | IPIPE_WIRED_MASK);
+
+ if (acknowledge == NULL) {
+ if ((modemask & IPIPE_SHARED_MASK) == 0) {
+ if (!ipipe_virtual_irq_p(irq)) {
+ /* Acknowledge handler unspecified for a hw
+ interrupt -- this is ok in non-shared
+ management mode, but we will force the use
+ of the Linux-defined handler instead. */
+ acknowledge = ipipe_root_domain->irqs[irq].acknowledge;
+ }
+ }
+ else {
+ /* A valid acknowledge handler to be called in shared mode
+ is required when declaring a shared IRQ. */
+ err = -EINVAL;
+ goto unlock_and_exit;
+ }
+ }
+
+ ipd->irqs[irq].handler = handler;
+ ipd->irqs[irq].cookie = cookie;
+ ipd->irqs[irq].acknowledge = acknowledge;
+ ipd->irqs[irq].control = modemask;
+
+ if (irq < NR_IRQS && handler != NULL && !ipipe_virtual_irq_p(irq)) {
+ __ipipe_enable_irqdesc(irq);
+
+ if ((modemask & IPIPE_ENABLE_MASK) != 0) {
+ if (ipd != ipipe_current_domain) {
+ /* IRQ enable/disable state is domain-sensitive, so we may
+ not change it for another domain. What is allowed
+ however is forcing some domain to handle an interrupt
+ source, by passing the proper 'ipd' descriptor which
+ thus may be different from ipipe_current_domain. */
+ err = -EPERM;
+ goto unlock_and_exit;
+ }
+
+ __ipipe_enable_irq(irq);
+ }
+ }
+
+ err = 0;
+
+ unlock_and_exit:
+
+ spin_unlock_irqrestore_hw(&__ipipe_pipelock, flags);
+
+ return err;
+}
+
+/* ipipe_control_irq() -- Change modes of a pipelined interrupt for
+ * the current domain. */
+
+int ipipe_control_irq(unsigned irq, unsigned clrmask, unsigned setmask)
+{
+ unsigned long flags;
+
+ if (irq >= IPIPE_NR_IRQS)
+ return -EINVAL;
+
+ if (ipipe_current_domain->irqs[irq].control & IPIPE_SYSTEM_MASK)
+ return -EPERM;
+
+ if (((setmask | clrmask) & IPIPE_SHARED_MASK) != 0)
+ return -EINVAL;
+
+ if (ipipe_current_domain->irqs[irq].handler == NULL)
+ setmask &= ~(IPIPE_HANDLE_MASK | IPIPE_STICKY_MASK);
+
+ if ((setmask & IPIPE_STICKY_MASK) != 0)
+ setmask |= IPIPE_HANDLE_MASK;
+
+ if ((clrmask & (IPIPE_HANDLE_MASK | IPIPE_STICKY_MASK)) != 0) /* If one goes, both go. */
+ clrmask |= (IPIPE_HANDLE_MASK | IPIPE_STICKY_MASK);
+
+ spin_lock_irqsave_hw(&__ipipe_pipelock, flags);
+
+ ipipe_current_domain->irqs[irq].control &= ~clrmask;
+ ipipe_current_domain->irqs[irq].control |= setmask;
+
+ if ((setmask & IPIPE_ENABLE_MASK) != 0)
+ __ipipe_enable_irq(irq);
+ else if ((clrmask & IPIPE_ENABLE_MASK) != 0)
+ __ipipe_disable_irq(irq);
+
+ spin_unlock_irqrestore_hw(&__ipipe_pipelock, flags);
+
+ return 0;
+}
+
+/* __ipipe_dispatch_event() -- Low-level event dispatcher. */
+
+int fastcall __ipipe_dispatch_event (unsigned event, void *data)
+{
+extern void *ipipe_irq_handler; void *handler; if (ipipe_irq_handler != __ipipe_handle_irq && (handler = ipipe_root_domain->evhand[event])) { return ((int (*)(unsigned long, void *))handler)(event, data); } else {
+ struct ipipe_domain *start_domain, *this_domain, *next_domain;
+ ipipe_event_handler_t evhand;
+ struct list_head *pos, *npos;
+ unsigned long flags;
+ ipipe_declare_cpuid;
+ int propagate = 1;
+
+ ipipe_lock_cpu(flags);
+
+ start_domain = this_domain = ipipe_percpu_domain[cpuid];
+
+ list_for_each_safe(pos,npos,&__ipipe_pipeline) {
+
+ /*
+ * Note: Domain migration may occur while running
+ * event or interrupt handlers, in which case the
+ * current register set is going to be recycled for a
+ * different domain than the initiating one. We do
+ * care for that, always tracking the current domain
+ * descriptor upon return from those handlers.
+ */
+ next_domain = list_entry(pos,struct ipipe_domain,p_link);
+
+ /*
+ * Keep a cached copy of the handler's address since
+ * ipipe_catch_event() may clear it under our feet.
+ */
+
+ evhand = next_domain->evhand[event];
+
+ if (evhand != NULL) {
+ ipipe_percpu_domain[cpuid] = next_domain;
+ next_domain->cpudata[cpuid].evsync |= (1LL << event);
+ ipipe_unlock_cpu(flags);
+ propagate = !evhand(event,start_domain,data);
+ ipipe_lock_cpu(flags);
+ next_domain->cpudata[cpuid].evsync &= ~(1LL << event);
+ if (ipipe_percpu_domain[cpuid] != next_domain)
+ this_domain = ipipe_percpu_domain[cpuid];
+ }
+
+ if (next_domain != ipipe_root_domain && /* NEVER sync the root stage here. */
+ next_domain->cpudata[cpuid].irq_pending_hi != 0 &&
+ !test_bit(IPIPE_STALL_FLAG,&next_domain->cpudata[cpuid].status)) {
+ ipipe_percpu_domain[cpuid] = next_domain;
+ __ipipe_sync_pipeline(IPIPE_IRQMASK_ANY);
+ ipipe_load_cpuid();
+ if (ipipe_percpu_domain[cpuid] != next_domain)
+ this_domain = ipipe_percpu_domain[cpuid];
+ }
+
+ ipipe_percpu_domain[cpuid] = this_domain;
+
+ if (next_domain == this_domain || !propagate)
+ break;
+ }
+
+ ipipe_unlock_cpu(flags);
+
+ return !propagate;
+} }
+
+/*
+ * __ipipe_dispatch_wired -- Wired interrupt dispatcher. Wired
+ * interrupts are immediately and unconditionally delivered to the
+ * domain heading the pipeline upon receipt, and such domain must have
+ * been registered as an invariant head for the system (priority ==
+ * IPIPE_HEAD_PRIORITY). The motivation for using wired interrupts is
+ * to get an extra-fast dispatching path for those IRQs, by relying on
+ * a straightforward logic based on assumptions that must always be
+ * true for invariant head domains. The following assumptions are
+ * made when dealing with such interrupts:
+ *
+ * 1- Wired interrupts are purely dynamic, i.e. the decision to
+ * propagate them down the pipeline must be done from the head domain
+ * ISR.
+ * 2- Wired interrupts cannot be shared or sticky.
+ * 3- The root domain cannot be an invariant pipeline head, in
+ * consequence of what the root domain cannot handle wired
+ * interrupts.
+ * 4- Wired interrupts must have a valid acknowledge handler for the
+ * head domain (if needed), and in any case, must not rely on handlers
+ * provided by lower priority domains during the acknowledge cycle
+ * (see __ipipe_handle_irq).
+ *
+ * Called with hw interrupts off.
+ */
+int fastcall __ipipe_dispatch_wired(struct ipipe_domain *head, unsigned irq)
+{
+ struct ipcpudata *cpudata;
+ struct ipipe_domain *old;
+ ipipe_declare_cpuid;
+
+ ipipe_load_cpuid();
+
+ if (head->irqs[irq].acknowledge != NULL)
+ head->irqs[irq].acknowledge(irq);
+
+ cpudata = &head->cpudata[cpuid];
+ cpudata->irq_counters[irq].total_hits++;
+
+ if (test_bit(IPIPE_LOCK_FLAG, &head->irqs[irq].control)) {
+ /* If we can't process this IRQ right now, we must
+ * mark it as pending, so that it will get played
+ * during normal log sync when the corresponding
+ * interrupt source is eventually unlocked. */
+ cpudata->irq_counters[irq].pending_hits++;
+ return 0;
+ }
+
+ if (test_bit(IPIPE_STALL_FLAG, &cpudata->status)) {
+ cpudata->irq_counters[irq].pending_hits++;
+ __ipipe_set_irq_bit(head, cpuid, irq);
+ return 0;
+ }
+
+ old = ipipe_percpu_domain[cpuid];
+ ipipe_percpu_domain[cpuid] = head; /* Switch to the head domain. */
+
+ __set_bit(IPIPE_STALL_FLAG, &cpudata->status);
+ head->irqs[irq].handler(irq,head->irqs[irq].cookie); /* Call the ISR. */
+ __ipipe_run_irqtail();
+ __clear_bit(IPIPE_STALL_FLAG, &cpudata->status);
+
+ /* We expect the caller to start a complete pipeline walk upon
+ * return, so that propagated interrupts will get played. */
+
+ if (ipipe_percpu_domain[cpuid] == head)
+ ipipe_percpu_domain[cpuid] = old; /* Back to the preempted domain. */
+
+ return 1;
+}
+
+/*
+ * __ipipe_sync_stage() -- Flush the pending IRQs for the current
+ * domain (and processor). This routine flushes the interrupt log
+ * (see "Optimistic interrupt protection" from D. Stodolsky et al. for
+ * more on the deferred interrupt scheme). Every interrupt that
+ * occurred while the pipeline was stalled gets played. WARNING:
+ * callers on SMP boxen should always check for CPU migration on
+ * return of this routine. One can control the kind of interrupts
+ * which are going to be sync'ed using the syncmask
+ * parameter. IPIPE_IRQMASK_ANY plays them all, IPIPE_IRQMASK_VIRT
+ * plays virtual interrupts only.
+ *
+ * This routine must be called with hw interrupts off.
+ */
+void fastcall __ipipe_sync_stage(unsigned long syncmask)
+{
+ unsigned long mask, submask;
+ struct ipcpudata *cpudata;
+ struct ipipe_domain *ipd;
+ ipipe_declare_cpuid;
+ int level, rank;
+ unsigned irq;
+
+ ipipe_load_cpuid();
+ ipd = ipipe_percpu_domain[cpuid];
+ cpudata = &ipd->cpudata[cpuid];
+
+ if (__test_and_set_bit(IPIPE_SYNC_FLAG, &cpudata->status))
+ return;
+
+ /*
+ * The policy here is to keep the dispatching code interrupt-free
+ * by stalling the current stage. If the upper domain handler
+ * (which we call) wants to re-enable interrupts while in a safe
+ * portion of the code (e.g. SA_INTERRUPT flag unset for Linux's
+ * sigaction()), it will have to unstall (then stall again before
+ * returning to us!) the stage when it sees fit.
+ */
+ while ((mask = (cpudata->irq_pending_hi & syncmask)) != 0) {
+ level = __ipipe_ffnz(mask);
+
+ while ((submask = cpudata->irq_pending_lo[level]) != 0) {
+ rank = __ipipe_ffnz(submask);
+ irq = (level << IPIPE_IRQ_ISHIFT) + rank;
+
+ if (test_bit(IPIPE_LOCK_FLAG, &ipd->irqs[irq].control)) {
+ __clear_bit(rank, &cpudata->irq_pending_lo[level]);
+ continue;
+ }
+
+ if (--cpudata->irq_counters[irq].pending_hits == 0) {
+ __clear_bit(rank, &cpudata->irq_pending_lo[level]);
+ if (cpudata->irq_pending_lo[level] == 0)
+ __clear_bit(level, &cpudata->irq_pending_hi);
+ }
+
+ __set_bit(IPIPE_STALL_FLAG, &cpudata->status);
+ __ipipe_run_isr(ipd, irq, cpuid);
+#ifdef CONFIG_SMP
+ {
+ int _cpuid = ipipe_processor_id();
+
+ if (_cpuid != cpuid) { /* Handle CPU migration. */
+ /*
+ * We expect any domain to clear the SYNC bit each
+ * time it switches in a new task, so that preemptions
+ * and/or CPU migrations (in the SMP case) over the
+ * ISR do not lock out the log syncer for some
+ * indefinite amount of time. In the Linux case,
+ * schedule() handles this (see kernel/sched.c). For
+ * this reason, we don't bother clearing it here for
+ * the source CPU in the migration handling case,
+ * since it must have scheduled another task in by
+ * now.
+ */
+ cpuid = _cpuid;
+ cpudata = &ipd->cpudata[cpuid];
+ __set_bit(IPIPE_SYNC_FLAG, &cpudata->status);
+ }
+ }
+#endif /* CONFIG_SMP */
+
+ __clear_bit(IPIPE_STALL_FLAG, &cpudata->status);
+ }
+ }
+
+ __clear_bit(IPIPE_SYNC_FLAG, &cpudata->status);
+}
+
+#ifdef CONFIG_PROC_FS
+
+#include <linux/proc_fs.h>
+
+static struct proc_dir_entry *ipipe_proc_root;
+
+static int __ipipe_version_info_proc(char *page,
+ char **start,
+ off_t off, int count, int *eof, void *data)
+{
+ int len = sprintf(page, "%s\n", IPIPE_VERSION_STRING);
+
+ len -= off;
+
+ if (len <= off + count)
+ *eof = 1;
+
+ *start = page + off;
+
+ if(len > count)
+ len = count;
+
+ if(len < 0)
+ len = 0;
+
+ return len;
+}
+
+static int __ipipe_common_info_proc(char *page,
+ char **start,
+ off_t off, int count, int *eof, void *data)
+{
+ struct ipipe_domain *ipd = (struct ipipe_domain *)data;
+ unsigned long ctlbits;
+ unsigned irq, _irq;
+ char *p = page;
+ int len;
+
+ spin_lock(&__ipipe_pipelock);
+
+ if (test_bit(IPIPE_AHEAD_FLAG,&ipd->flags))
+ p += sprintf(p, "Invariant head");
+ else
+ p += sprintf(p, "Priority=%d", ipd->priority);
+
+ p += sprintf(p, ", Id=0x%.8x\n", ipd->domid);
+
+ irq = 0;
+
+ while (irq < IPIPE_NR_IRQS) {
+ ctlbits =
+ (ipd->irqs[irq].
+ control & (IPIPE_HANDLE_MASK | IPIPE_PASS_MASK |
+ IPIPE_STICKY_MASK | IPIPE_WIRED_MASK));
+ if (irq >= IPIPE_NR_XIRQS && !ipipe_virtual_irq_p(irq)) {
+ /*
+ * There might be a hole between the last external
+ * IRQ and the first virtual one; skip it.
+ */
+ irq++;
+ continue;
+ }
+
+ if (ipipe_virtual_irq_p(irq)
+ && !test_bit(irq - IPIPE_VIRQ_BASE,
+ &__ipipe_virtual_irq_map)) {
+ /* Non-allocated virtual IRQ; skip it. */
+ irq++;
+ continue;
+ }
+
+ /*
+ * Attempt to group consecutive IRQ numbers having the
+ * same virtualization settings in a single line.
+ */
+
+ _irq = irq;
+
+ while (++_irq < IPIPE_NR_IRQS) {
+ if (ipipe_virtual_irq_p(_irq) !=
+ ipipe_virtual_irq_p(irq)
+ || (ipipe_virtual_irq_p(_irq)
+ && !test_bit(_irq - IPIPE_VIRQ_BASE,
+ &__ipipe_virtual_irq_map))
+ || ctlbits != (ipd->irqs[_irq].
+ control & (IPIPE_HANDLE_MASK |
+ IPIPE_PASS_MASK |
+ IPIPE_STICKY_MASK)))
+ break;
+ }
+
+ if (_irq == irq + 1)
+ p += sprintf(p, "irq%u: ", irq);
+ else
+ p += sprintf(p, "irq%u-%u: ", irq, _irq - 1);
+
+ /*
+ * Statuses are as follows:
+ * o "accepted" means handled _and_ passed down the pipeline.
+ * o "grabbed" means handled, but the interrupt might be
+ * terminated _or_ passed down the pipeline depending on
+ * what the domain handler asks for to the I-pipe.
+ * o "wired" is basically the same as "grabbed", except that
+ * the interrupt is unconditionally delivered to an invariant
+ * pipeline head domain.
+ * o "passed" means unhandled by the domain but passed
+ * down the pipeline.
+ * o "discarded" means unhandled and _not_ passed down the
+ * pipeline. The interrupt merely disappears from the
+ * current domain down to the end of the pipeline.
+ */
+ if (ctlbits & IPIPE_HANDLE_MASK) {
+ if (ctlbits & IPIPE_PASS_MASK)
+ p += sprintf(p, "accepted");
+ else if (ctlbits & IPIPE_WIRED_MASK)
+ p += sprintf(p, "wired");
+ else
+ p += sprintf(p, "grabbed");
+ } else if (ctlbits & IPIPE_PASS_MASK)
+ p += sprintf(p, "passed");
+ else
+ p += sprintf(p, "discarded");
+
+ if (ctlbits & IPIPE_STICKY_MASK)
+ p += sprintf(p, ", sticky");
+
+ if (ipipe_virtual_irq_p(irq))
+ p += sprintf(p, ", virtual");
+
+ p += sprintf(p, "\n");
+
+ irq = _irq;
+ }
+
+ spin_unlock(&__ipipe_pipelock);
+
+ len = p - page;
+
+ if (len <= off + count)
+ *eof = 1;
+
+ *start = page + off;
+
+ len -= off;
+
+ if (len > count)
+ len = count;
+
+ if (len < 0)
+ len = 0;
+
+ return len;
+}
+
+void __ipipe_add_domain_proc(struct ipipe_domain *ipd)
+{
+ create_proc_read_entry(ipd->name,0444,ipipe_proc_root,&__ipipe_common_info_proc,ipd);
+}
+
+void __ipipe_remove_domain_proc(struct ipipe_domain *ipd)
+{
+ remove_proc_entry(ipd->name,ipipe_proc_root);
+}
+
+void ipipe_init_proc(void)
+{
+ ipipe_proc_root = create_proc_entry("ipipe",S_IFDIR, 0);
+ create_proc_read_entry("version",0444,ipipe_proc_root,&__ipipe_version_info_proc,NULL);
+ __ipipe_add_domain_proc(ipipe_root_domain);
+}
+
+#endif /* CONFIG_PROC_FS */
+
+EXPORT_SYMBOL(ipipe_virtualize_irq);
+EXPORT_SYMBOL(ipipe_control_irq);
+EXPORT_SYMBOL(ipipe_suspend_domain);
+EXPORT_SYMBOL(ipipe_alloc_virq);
+EXPORT_SYMBOL(ipipe_stall_pipeline_from);
+EXPORT_SYMBOL(ipipe_test_and_stall_pipeline_from);
+EXPORT_SYMBOL(ipipe_unstall_pipeline_from);
+EXPORT_SYMBOL(ipipe_restore_pipeline_from);
+EXPORT_SYMBOL(ipipe_test_and_unstall_pipeline_from);
+EXPORT_SYMBOL(ipipe_unstall_pipeline_head);
+EXPORT_SYMBOL(__ipipe_restore_pipeline_head);
+EXPORT_SYMBOL(ipipe_percpu_domain);
+EXPORT_SYMBOL(ipipe_root);
+EXPORT_SYMBOL(ipipe_setscheduler_root);
+EXPORT_SYMBOL(ipipe_reenter_root);
+EXPORT_SYMBOL(__ipipe_unstall_root);
+EXPORT_SYMBOL(__ipipe_stall_root);
+EXPORT_SYMBOL(__ipipe_restore_root);
+EXPORT_SYMBOL(__ipipe_test_and_stall_root);
+EXPORT_SYMBOL(__ipipe_test_root);
+EXPORT_SYMBOL(__ipipe_dispatch_event);
+EXPORT_SYMBOL(__ipipe_dispatch_wired);
+EXPORT_SYMBOL(__ipipe_sync_stage);
+EXPORT_SYMBOL(__ipipe_pipeline);
+EXPORT_SYMBOL(__ipipe_pipelock);
+EXPORT_SYMBOL(__ipipe_virtual_irq_map);
diff -uNrp 2.4.35.5/kernel/ipipe/generic.c 2.4.35.5-i386-ipipe/kernel/ipipe/generic.c
--- 2.4.35.5/kernel/ipipe/generic.c 1970-01-01 01:00:00.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/ipipe/generic.c 2007-12-22 16:46:39.000000000 +0100
@@ -0,0 +1,443 @@
+/* -*- linux-c -*-
+ * linux/kernel/ipipe/generic.c
+ *
+ * Copyright (C) 2002-2005 Philippe Gerum.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, Inc., 675 Mass Ave, Cambridge MA 02139,
+ * USA; either version 2 of the License, or (at your option) any later
+ * version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Architecture-independent I-PIPE services.
+ */
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#ifdef CONFIG_PROC_FS
+#include <linux/proc_fs.h>
+#endif /* CONFIG_PROC_FS */
+#include <linux/interrupt.h>
+#include <asm/hw_irq.h>
+
+MODULE_DESCRIPTION("I-pipe");
+MODULE_LICENSE("GPL");
+
+static int __ipipe_ptd_key_count;
+
+static unsigned long __ipipe_ptd_key_map;
+
+/* ipipe_register_domain() -- Link a new domain to the pipeline. */
+
+int ipipe_register_domain(struct ipipe_domain *ipd,
+ struct ipipe_domain_attr *attr)
+{
+ struct list_head *pos;
+ unsigned long flags;
+
+ if (ipipe_current_domain != ipipe_root_domain) {
+ printk(KERN_WARNING
+ "I-pipe: Only the root domain may register a new domain.\n");
+ return -EPERM;
+ }
+
+ if (attr->priority == IPIPE_HEAD_PRIORITY &&
+ test_bit(IPIPE_AHEAD_FLAG,&__ipipe_pipeline_head()->flags))
+ return -EAGAIN; /* Cannot override current head. */
+
+ flags = ipipe_critical_enter(NULL);
+
+ list_for_each(pos, &__ipipe_pipeline) {
+ struct ipipe_domain *_ipd =
+ list_entry(pos, struct ipipe_domain, p_link);
+ if (_ipd->domid == attr->domid)
+ break;
+ }
+
+ ipipe_critical_exit(flags);
+
+ if (pos != &__ipipe_pipeline)
+ /* A domain with the given id already exists -- fail. */
+ return -EBUSY;
+
+ ipd->name = attr->name;
+ ipd->domid = attr->domid;
+ ipd->pdd = attr->pdd;
+ ipd->flags = 0;
+
+ if (attr->priority == IPIPE_HEAD_PRIORITY) {
+ ipd->priority = INT_MAX;
+ __set_bit(IPIPE_AHEAD_FLAG,&ipd->flags);
+ }
+ else
+ ipd->priority = attr->priority;
+
+ __ipipe_init_stage(ipd);
+
+ INIT_LIST_HEAD(&ipd->p_link);
+
+#ifdef CONFIG_PROC_FS
+ __ipipe_add_domain_proc(ipd);
+#endif /* CONFIG_PROC_FS */
+
+ flags = ipipe_critical_enter(NULL);
+
+ list_for_each(pos, &__ipipe_pipeline) {
+ struct ipipe_domain *_ipd =
+ list_entry(pos, struct ipipe_domain, p_link);
+ if (ipd->priority > _ipd->priority)
+ break;
+ }
+
+ list_add_tail(&ipd->p_link, pos);
+
+ ipipe_critical_exit(flags);
+
+ printk(KERN_WARNING "I-pipe: Domain %s registered.\n", ipd->name);
+
+ /*
+ * Finally, allow the new domain to perform its initialization
+ * chores.
+ */
+
+ if (attr->entry != NULL) {
+ ipipe_declare_cpuid;
+
+ ipipe_lock_cpu(flags);
+
+ ipipe_percpu_domain[cpuid] = ipd;
+ attr->entry();
+ ipipe_percpu_domain[cpuid] = ipipe_root_domain;
+
+ ipipe_load_cpuid(); /* Processor might have changed. */
+
+ if (ipipe_root_domain->cpudata[cpuid].irq_pending_hi != 0 &&
+ !test_bit(IPIPE_STALL_FLAG,
+ &ipipe_root_domain->cpudata[cpuid].status))
+ __ipipe_sync_stage(IPIPE_IRQMASK_ANY);
+
+ ipipe_unlock_cpu(flags);
+ }
+
+ return 0;
+}
+
+/* ipipe_unregister_domain() -- Remove a domain from the pipeline. */
+
+int ipipe_unregister_domain(struct ipipe_domain *ipd)
+{
+ unsigned long flags;
+
+ if (ipipe_current_domain != ipipe_root_domain) {
+ printk(KERN_WARNING
+ "I-pipe: Only the root domain may unregister a domain.\n");
+ return -EPERM;
+ }
+
+ if (ipd == ipipe_root_domain) {
+ printk(KERN_WARNING
+ "I-pipe: Cannot unregister the root domain.\n");
+ return -EPERM;
+ }
+#ifdef CONFIG_SMP
+ {
+ int nr_cpus = num_online_cpus(), _cpuid;
+ unsigned irq;
+
+ /*
+ * In the SMP case, wait for the logged events to drain on
+ * other processors before eventually removing the domain
+ * from the pipeline.
+ */
+
+ ipipe_unstall_pipeline_from(ipd);
+
+ flags = ipipe_critical_enter(NULL);
+
+ for (irq = 0; irq < IPIPE_NR_IRQS; irq++) {
+ clear_bit(IPIPE_HANDLE_FLAG, &ipd->irqs[irq].control);
+ clear_bit(IPIPE_STICKY_FLAG, &ipd->irqs[irq].control);
+ set_bit(IPIPE_PASS_FLAG, &ipd->irqs[irq].control);
+ }
+
+ ipipe_critical_exit(flags);
+
+ for (_cpuid = 0; _cpuid < nr_cpus; _cpuid++)
+ for (irq = 0; irq < IPIPE_NR_IRQS; irq++)
+ while (ipd->cpudata[_cpuid].irq_counters[irq].pending_hits > 0)
+ cpu_relax();
+ }
+#endif /* CONFIG_SMP */
+
+#ifdef CONFIG_PROC_FS
+ __ipipe_remove_domain_proc(ipd);
+#endif /* CONFIG_PROC_FS */
+
+ /*
+ * Simply remove the domain from the pipeline and we are almost done.
+ */
+
+ flags = ipipe_critical_enter(NULL);
+ list_del_init(&ipd->p_link);
+ ipipe_critical_exit(flags);
+
+ __ipipe_cleanup_domain(ipd);
+
+ printk(KERN_WARNING "I-pipe: Domain %s unregistered.\n", ipd->name);
+
+ return 0;
+}
+
+/*
+ * ipipe_propagate_irq() -- Force a given IRQ propagation on behalf of
+ * a running interrupt handler to the next domain down the pipeline.
+ * ipipe_schedule_irq() -- Does almost the same as above, but attempts
+ * to pend the interrupt for the current domain first.
+ */
+int fastcall __ipipe_schedule_irq(unsigned irq, struct list_head *head)
+{
+ struct list_head *ln;
+ unsigned long flags;
+ ipipe_declare_cpuid;
+
+ if (irq >= IPIPE_NR_IRQS ||
+ (ipipe_virtual_irq_p(irq)
+ && !test_bit(irq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map)))
+ return -EINVAL;
+
+ ipipe_lock_cpu(flags);
+
+ ln = head;
+
+ while (ln != &__ipipe_pipeline) {
+ struct ipipe_domain *ipd =
+ list_entry(ln, struct ipipe_domain, p_link);
+
+ if (test_bit(IPIPE_HANDLE_FLAG, &ipd->irqs[irq].control)) {
+ ipd->cpudata[cpuid].irq_counters[irq].total_hits++;
+ ipd->cpudata[cpuid].irq_counters[irq].pending_hits++;
+ __ipipe_set_irq_bit(ipd, cpuid, irq);
+ ipipe_unlock_cpu(flags);
+ return 1;
+ }
+
+ ln = ipd->p_link.next;
+ }
+
+ ipipe_unlock_cpu(flags);
+
+ return 0;
+}
+
+/* ipipe_free_virq() -- Release a virtual/soft interrupt. */
+
+int ipipe_free_virq(unsigned virq)
+{
+ if (!ipipe_virtual_irq_p(virq))
+ return -EINVAL;
+
+ clear_bit(virq - IPIPE_VIRQ_BASE, &__ipipe_virtual_irq_map);
+
+ return 0;
+}
+
+void ipipe_init_attr(struct ipipe_domain_attr *attr)
+{
+ attr->name = "anon";
+ attr->domid = 1;
+ attr->entry = NULL;
+ attr->priority = IPIPE_ROOT_PRIO;
+ attr->pdd = NULL;
+}
+
+/*
+ * ipipe_catch_event() -- Interpose or remove an event handler for a
+ * given domain.
+ */
+ipipe_event_handler_t ipipe_catch_event(struct ipipe_domain *ipd,
+ unsigned event,
+ ipipe_event_handler_t handler)
+{
+ ipipe_event_handler_t old_handler;
+ unsigned long flags;
+ int self = 0, cpuid;
+
+ if (event & IPIPE_EVENT_SELF) {
+ event &= ~IPIPE_EVENT_SELF;
+ self = 1;
+ }
+
+ if (event >= IPIPE_NR_EVENTS)
+ return NULL;
+
+ flags = ipipe_critical_enter(NULL);
+
+ if (!(old_handler = xchg(&ipd->evhand[event],handler))) {
+ if (handler) {
+ if (self)
+ ipd->evself |= (1LL << event);
+ else
+ __ipipe_event_monitors[event]++;
+ }
+ }
+ else if (!handler) {
+ if (ipd->evself & (1LL << event))
+ ipd->evself &= ~(1LL << event);
+ else
+ __ipipe_event_monitors[event]--;
+ } else if ((ipd->evself & (1LL << event)) && !self) {
+ __ipipe_event_monitors[event]++;
+ ipd->evself &= ~(1LL << event);
+ } else if (!(ipd->evself & (1LL << event)) && self) {
+ __ipipe_event_monitors[event]--;
+ ipd->evself |= (1LL << event);
+ }
+
+ ipipe_critical_exit(flags);
+
+ if (!handler && ipipe_root_domain_p) {
+ /*
+ * If we cleared a handler on behalf of the root
+ * domain, we have to wait for any current invocation
+ * to drain, since our caller might subsequently unmap
+ * the target domain. To this aim, this code
+ * synchronizes with __ipipe_dispatch_event(),
+ * guaranteeing that either the dispatcher sees a null
+ * handler in which case it discards the invocation
+ * (which also prevents from entering a livelock), or
+ * finds a valid handler and calls it. Symmetrically,
+ * ipipe_catch_event() ensures that the called code
+ * won't be unmapped under our feet until the event
+ * synchronization flag is cleared for the given event
+ * on all CPUs.
+ */
+
+ for_each_online_cpu(cpuid) {
+ while (ipd->cpudata[cpuid].evsync & (1LL << event)) {
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(HZ / 50);
+ }
+ }
+ }
+
+ return old_handler;
+}
+
+cpumask_t ipipe_set_irq_affinity (unsigned irq, cpumask_t cpumask)
+{
+#ifdef CONFIG_SMP
+ if (irq >= IPIPE_NR_XIRQS)
+ /* Allow changing affinity of external IRQs only. */
+ return CPU_MASK_NONE;
+
+ if (num_online_cpus() > 1)
+ /* Allow changing affinity of external IRQs only. */
+ return __ipipe_set_irq_affinity(irq,cpumask);
+#endif /* CONFIG_SMP */
+
+ return CPU_MASK_NONE;
+}
+
+int fastcall ipipe_send_ipi (unsigned ipi, cpumask_t cpumask)
+
+{
+#ifdef CONFIG_SMP
+ switch (ipi) {
+
+ case IPIPE_SERVICE_IPI0:
+ case IPIPE_SERVICE_IPI1:
+ case IPIPE_SERVICE_IPI2:
+ case IPIPE_SERVICE_IPI3:
+
+ break;
+
+ default:
+
+ return -EINVAL;
+ }
+
+ return __ipipe_send_ipi(ipi,cpumask);
+#endif /* CONFIG_SMP */
+
+ return -EINVAL;
+}
+
+int ipipe_alloc_ptdkey (void)
+{
+ unsigned long flags;
+ int key = -1;
+
+ spin_lock_irqsave_hw(&__ipipe_pipelock,flags);
+
+ if (__ipipe_ptd_key_count < IPIPE_ROOT_NPTDKEYS) {
+ key = ffz(__ipipe_ptd_key_map);
+ set_bit(key,&__ipipe_ptd_key_map);
+ __ipipe_ptd_key_count++;
+ }
+
+ spin_unlock_irqrestore_hw(&__ipipe_pipelock,flags);
+
+ return key;
+}
+
+int ipipe_free_ptdkey (int key)
+{
+ unsigned long flags;
+
+ if (key < 0 || key >= IPIPE_ROOT_NPTDKEYS)
+ return -EINVAL;
+
+ spin_lock_irqsave_hw(&__ipipe_pipelock,flags);
+
+ if (test_and_clear_bit(key,&__ipipe_ptd_key_map))
+ __ipipe_ptd_key_count--;
+
+ spin_unlock_irqrestore_hw(&__ipipe_pipelock,flags);
+
+ return 0;
+}
+
+int fastcall ipipe_set_ptd (int key, void *value)
+
+{
+ if (key < 0 || key >= IPIPE_ROOT_NPTDKEYS)
+ return -EINVAL;
+
+ current->ptd[key] = value;
+
+ return 0;
+}
+
+void *fastcall ipipe_get_ptd (int key)
+
+{
+ if (key < 0 || key >= IPIPE_ROOT_NPTDKEYS)
+ return NULL;
+
+ return current->ptd[key];
+}
+
+EXPORT_SYMBOL(ipipe_register_domain);
+EXPORT_SYMBOL(ipipe_unregister_domain);
+EXPORT_SYMBOL(ipipe_free_virq);
+EXPORT_SYMBOL(ipipe_init_attr);
+EXPORT_SYMBOL(ipipe_catch_event);
+EXPORT_SYMBOL(ipipe_alloc_ptdkey);
+EXPORT_SYMBOL(ipipe_free_ptdkey);
+EXPORT_SYMBOL(ipipe_set_ptd);
+EXPORT_SYMBOL(ipipe_get_ptd);
+EXPORT_SYMBOL(ipipe_set_irq_affinity);
+EXPORT_SYMBOL(ipipe_send_ipi);
+EXPORT_SYMBOL(__ipipe_schedule_irq);
diff -uNrp 2.4.35.5/kernel/printk.c 2.4.35.5-i386-ipipe/kernel/printk.c
--- 2.4.35.5/kernel/printk.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/printk.c 2007-12-22 16:46:39.000000000 +0100
@@ -409,7 +409,88 @@ static void emit_log_char(char c)
* then changes console_loglevel may break. This is because console_loglevel
* is inspected when the actual printing occurs.
*/
+#ifdef CONFIG_IPIPE
+
+static ipipe_spinlock_t __ipipe_printk_lock = IPIPE_SPIN_LOCK_UNLOCKED;
+
+static int __ipipe_printk_fill;
+
+static char __ipipe_printk_buf[LOG_BUF_LEN];
+
+static int do_printk(const char *fmt, ...);
+
+void __ipipe_flush_printk (unsigned virq, void *cookie)
+{
+ char *p = __ipipe_printk_buf;
+ int len, lmax, out = 0;
+ unsigned long flags;
+
+ goto start;
+
+ do {
+ spin_unlock_irqrestore_hw(&__ipipe_printk_lock,flags);
+ start:
+ lmax = __ipipe_printk_fill;
+ while (out < lmax) {
+ len = strlen(p) + 1;
+ do_printk("%s",p);
+ p += len;
+ out += len;
+ }
+ spin_lock_irqsave_hw(&__ipipe_printk_lock,flags);
+ }
+ while (__ipipe_printk_fill != lmax);
+
+ __ipipe_printk_fill = 0;
+
+ spin_unlock_irqrestore_hw(&__ipipe_printk_lock,flags);
+}
+
+int vscnprintf(char *buf, size_t size, const char *fmt, va_list args)
+{
+ int i = vsnprintf(buf,size,fmt,args);
+ return (i >= size) ? (size - 1) : i;
+}
+
+asmlinkage int printk(const char *fmt, ...)
+{
+ unsigned long flags, oldcount;
+ int r, fbytes;
+ va_list args;
+
+ va_start(args, fmt);
+
+ spin_lock_irqsave_hw(&__ipipe_printk_lock,flags);
+
+ oldcount = __ipipe_printk_fill;
+ fbytes = LOG_BUF_LEN - __ipipe_printk_fill;
+
+ if (fbytes > 1) {
+ r = vscnprintf(__ipipe_printk_buf + __ipipe_printk_fill,
+ fbytes, fmt, args) + 1; /* account for the null byte */
+ __ipipe_printk_fill += r;
+ } else
+ r = 0;
+
+ spin_unlock_irqrestore_hw(&__ipipe_printk_lock,flags);
+
+ if (ipipe_current_domain == ipipe_root_domain ||
+ test_bit(IPIPE_SPRINTK_FLAG,&ipipe_current_domain->flags) ||
+ oops_in_progress) {
+ __ipipe_flush_printk(__ipipe_printk_virq, NULL);
+ }
+ else if (oldcount == 0)
+ ipipe_trigger_irq(__ipipe_printk_virq);
+
+ va_end(args);
+
+ return r;
+}
+
+static int do_printk(const char *fmt, ...)
+#else /* !CONFIG_IPIPE */
asmlinkage int printk(const char *fmt, ...)
+#endif /* CONFIG_IPIPE */
{
va_list args;
unsigned long flags;
diff -uNrp 2.4.35.5/kernel/sched.c 2.4.35.5-i386-ipipe/kernel/sched.c
--- 2.4.35.5/kernel/sched.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/sched.c 2007-12-22 16:46:39.000000000 +0100
@@ -355,6 +355,8 @@ static inline int try_to_wake_up(struct
* We want the common case fall through straight, thus the goto.
*/
spin_lock_irqsave(&runqueue_lock, flags);
+ if (p->state & TASK_NOWAKEUP)
+ goto out;
p->state = TASK_RUNNING;
if (task_on_runqueue(p))
goto out;
@@ -531,9 +533,73 @@ needs_resched:
asmlinkage void schedule_tail(struct task_struct *prev)
{
+#ifdef CONFIG_IPIPE
+ local_irq_disable();
+ local_irq_enable_hw();
+#endif /* CONFIG_IPIPE */
__schedule_tail(prev);
+ ipipe_init_notify(current);
+#ifdef CONFIG_IPIPE
+ local_irq_enable();
+#endif /* CONFIG_IPIPE */
+}
+
+static struct delayed_mmreq {
+ int in;
+ int out;
+ int count;
+#define MAX_DELAYED_MM 32 /* need ^2 here. */
+ struct mm_struct *mm[MAX_DELAYED_MM];
+} delayed_mmtab[NR_CPUS];
+
+static void __ipipe_delay_mmdrop (struct task_struct *prev)
+{
+ if (!prev->mm) {
+ struct delayed_mmreq *p = delayed_mmtab + prev->processor;
+ struct mm_struct *oldmm = prev->active_mm;
+ BUG_ON(p->count >= MAX_DELAYED_MM);
+ /*
+ * Prevent the mm from being dropped in schedule()
+ * since this could cause 1) large latencies to high
+ * priority domains hijacking Linux tasks, 2) subtle
+ * mm recycling error at task exit due to
+ * co-scheduling issues, then pend a request to drop
+ * it later in __ipipe_mmdrop_sync() when Linux is
+ * back in control.
+ */
+ atomic_inc(&oldmm->mm_count);
+ p->mm[p->in] = oldmm;
+ p->in = (p->in + 1) & (MAX_DELAYED_MM - 1);
+ p->count++;
+ }
+}
+
+static void __ipipe_sync_mmdrop (void)
+{
+ struct delayed_mmreq *p = delayed_mmtab + smp_processor_id();
+
+ while (p->out != p->in) {
+ struct mm_struct *oldmm = p->mm[p->out];
+ mmdrop(oldmm);
+ p->out = (p->out + 1) & (MAX_DELAYED_MM - 1);
+ p->count--;
+ }
+}
+
+struct task_struct *context_switch(struct task_struct *prev, struct task_struct
+*next)
+{
+#ifdef CONFIG_IPIPE
+ next->ptd[IPIPE_ROOT_NPTDKEYS - 1] = prev;
+#endif /* CONFIG_IPIPE */
+ switch_to(prev, next, prev);
+ return prev;
}
+#define EXPORT_SYMTAB
+#include <linux/module.h>
+EXPORT_SYMBOL(context_switch);
+
/*
* 'schedule()' is the scheduler function. It's a very simple and nice
* scheduler: it's not perfect, but certainly works for most things.
@@ -668,7 +734,8 @@ repeat_schedule:
* but prev is set to (the just run) 'last' process by switch_to().
* This might sound slightly confusing but makes tons of sense.
*/
- prepare_to_switch();
+ prepare_to_switch(next);
+ __ipipe_delay_mmdrop(prev);
{
struct mm_struct *mm = next->mm;
struct mm_struct *oldmm = prev->active_mm;
@@ -692,7 +759,10 @@ repeat_schedule:
* This just switches the register state and the
* stack.
*/
- switch_to(prev, next, prev);
+ prev = context_switch(prev, next); // switch_to(prev, next, prev);
+ if (task_hijacked(prev))
+ return; __ipipe_dispatch_event(IPIPE_FIRST_EVENT - 2, 0);
+ __ipipe_sync_mmdrop();
__schedule_tail(prev);
same_process:
@@ -991,6 +1061,7 @@ static int setscheduler(pid_t pid, int p
retval = 0;
p->policy = policy;
p->rt_priority = lp.sched_priority;
+ ipipe_setsched_notify(p);
current->need_resched = 1;
@@ -1395,3 +1466,34 @@ void __init sched_init(void)
atomic_inc(&init_mm.mm_count);
enter_lazy_tlb(&init_mm, current, cpu);
}
+
+#ifdef CONFIG_IPIPE
+
+int ipipe_setscheduler_root (struct task_struct *p, int policy, int prio)
+{
+ read_lock_irq(&tasklist_lock);
+ spin_lock(&runqueue_lock);
+
+ p->policy = policy;
+ p->rt_priority = prio;
+ current->need_resched = 1;
+
+ spin_unlock(&runqueue_lock);
+ read_unlock_irq(&tasklist_lock);
+
+ return 0;
+}
+
+int ipipe_reenter_root (struct task_struct *prev, int policy, int prio)
+{
+ __schedule_tail(prev);
+ reacquire_kernel_lock(current);
+ local_irq_enable();
+
+ if (current->policy != policy || current->rt_priority != prio)
+ return ipipe_setscheduler_root(current,policy,prio);
+
+ return 0;
+}
+
+#endif /* CONFIG_IPIPE */
diff -uNrp 2.4.35.5/kernel/signal.c 2.4.35.5-i386-ipipe/kernel/signal.c
--- 2.4.35.5/kernel/signal.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/kernel/signal.c 2007-12-22 16:46:39.000000000 +0100
@@ -506,7 +506,8 @@ static int send_signal(int sig, struct s
static inline void signal_wake_up(struct task_struct *t)
{
t->sigpending = 1;
-
+ ipipe_sigwake_notify(t); /* sigpending must be set first. */
+
#ifdef CONFIG_SMP
/*
* If the task is running on a different CPU
diff -uNrp 2.4.35.5/mm/vmalloc.c 2.4.35.5-i386-ipipe/mm/vmalloc.c
--- 2.4.35.5/mm/vmalloc.c 2007-12-17 00:16:04.000000000 +0100
+++ 2.4.35.5-i386-ipipe/mm/vmalloc.c 2007-12-22 16:46:39.000000000 +0100
@@ -165,6 +165,7 @@ static inline int __vmalloc_area_pages (
dir = pgd_offset_k(address);
spin_lock(&init_mm.page_table_lock);
do {
+ pgd_t olddir = *dir;
pmd_t *pmd;
pmd = pmd_alloc(&init_mm, dir, address);
@@ -174,6 +175,9 @@ static inline int __vmalloc_area_pages (
if (alloc_area_pmd(pmd, address, end - address, gfp_mask, prot, pages))
goto err; // The kernel NEVER reclaims pmds, so no need to undo pmd_alloc() here
+ if (pgd_val(olddir) != pgd_val(*dir))
+ set_pgdir(address,*dir);
+
address = (address + PGDIR_SIZE) & PGDIR_MASK;
dir++;
} while (address && (address < end));
|