/usr/src/gcc-5/debian/patches/gcc-linaro-revert-r234641.diff is in gcc-5-source 5.3.1-14ubuntu2.
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 | # DP: Revert r234641 for gcc-linaro, which removed support for %( and %) output modifiers.
Index: b/src/gcc/ChangeLog
===================================================================
--- a/src/gcc/ChangeLog
+++ b/src/gcc/ChangeLog
@@ -188,11 +188,6 @@
* varasm.c (output_constructor_regular_field): Flush bitfield
earlier. Assert we don't want to move backwards.
-2016-03-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * config/arm/sync.md (arm_atomic_loaddi2_ldrd): Fix output template
- for non-unified syntax.
-
2016-03-31 Kirill Yukhin <kirill.yukhin@intel.com>
PR target/70453
Index: b/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c
===================================================================
--- a/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c
+++ b/src/gcc/testsuite/gcc.target/arm/atomic_loaddi_relaxed_cond.c
@@ -1,20 +0,0 @@
-/* { dg-do assemble } */
-/* { dg-options "-std=c11 -O" } */
-/* { dg-require-effective-target arm_arch_v8a_ok } */
-/* { dg-add-options arm_arch_v8a } */
-
-/* Check that if we conditionalise the atomic load we put the condition
- code in the right place to create valid assembly. */
-
-#include <stdatomic.h>
-
-atomic_ullong foo;
-int glob;
-
-int
-main (int argc, char *argv[])
-{
- if (argc > 2)
- atomic_load_explicit (&foo, memory_order_relaxed);
- return glob;
-}
Index: b/src/gcc/testsuite/ChangeLog
===================================================================
--- a/src/gcc/testsuite/ChangeLog
+++ b/src/gcc/testsuite/ChangeLog
@@ -185,10 +185,6 @@
PR c++/70393
* g++.dg/cpp0x/constexpr-virtual6.C: New.
-2016-03-31 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
-
- * gcc.target/arm/atomic_loaddi_relaxed_cond.c: New test.
-
2016-03-31 Kirill Yukhin <kirill.yukhin@intel.com>
PR target/70453
Index: b/src/gcc/config/arm/sync.md
===================================================================
--- a/src/gcc/config/arm/sync.md
+++ b/src/gcc/config/arm/sync.md
@@ -104,7 +104,7 @@
[(match_operand:DI 1 "arm_sync_memory_operand" "Q")]
VUNSPEC_LDRD_ATOMIC))]
"ARM_DOUBLEWORD_ALIGN && TARGET_HAVE_LPAE"
- "ldr%(d%)\t%0, %H0, %C1"
+ "ldrd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
|