/usr/msp430/include/msp430g2112.h is in msp430mcu 20120406-2.
This file is owned by root:root, with mode 0o644.
The actual contents of the file can be viewed below.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 | /* ============================================================================ */
/* Copyright (c) 2012, Texas Instruments Incorporated */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following conditions */
/* are met: */
/* */
/* * Redistributions of source code must retain the above copyright */
/* notice, this list of conditions and the following disclaimer. */
/* */
/* * Redistributions in binary form must reproduce the above copyright */
/* notice, this list of conditions and the following disclaimer in the */
/* documentation and/or other materials provided with the distribution. */
/* */
/* * Neither the name of Texas Instruments Incorporated nor the names of */
/* its contributors may be used to endorse or promote products derived */
/* from this software without specific prior written permission. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ============================================================================ */
/********************************************************************
*
* Standard register and bit definitions for the Texas Instruments
* MSP430 microcontroller.
*
* This file supports assembler and C development for
* MSP430G2112 devices.
*
* Texas Instruments, Version 1.0
*
* Rev. 1.0, Setup
*
********************************************************************/
#ifndef __MSP430G2112
#define __MSP430G2112
#define __MSP430_HEADER_VERSION__ 1064
#define __MSP430_TI_HEADERS__
#ifdef __cplusplus
extern "C" {
#endif
#include <iomacros.h>
/************************************************************
* STANDARD BITS
************************************************************/
#define BIT0 (0x0001)
#define BIT1 (0x0002)
#define BIT2 (0x0004)
#define BIT3 (0x0008)
#define BIT4 (0x0010)
#define BIT5 (0x0020)
#define BIT6 (0x0040)
#define BIT7 (0x0080)
#define BIT8 (0x0100)
#define BIT9 (0x0200)
#define BITA (0x0400)
#define BITB (0x0800)
#define BITC (0x1000)
#define BITD (0x2000)
#define BITE (0x4000)
#define BITF (0x8000)
/************************************************************
* STATUS REGISTER BITS
************************************************************/
#define C (0x0001)
#define Z (0x0002)
#define N (0x0004)
#define V (0x0100)
#define GIE (0x0008)
#define CPUOFF (0x0010)
#define OSCOFF (0x0020)
#define SCG0 (0x0040)
#define SCG1 (0x0080)
/* Low Power Modes coded with Bits 4-7 in SR */
#ifndef __STDC__ /* Begin #defines for assembler */
#define LPM0 (CPUOFF)
#define LPM1 (SCG0+CPUOFF)
#define LPM2 (SCG1+CPUOFF)
#define LPM3 (SCG1+SCG0+CPUOFF)
#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
/* End #defines for assembler */
#else /* Begin #defines for C */
#define LPM0_bits (CPUOFF)
#define LPM1_bits (SCG0+CPUOFF)
#define LPM2_bits (SCG1+CPUOFF)
#define LPM3_bits (SCG1+SCG0+CPUOFF)
#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
#include "in430.h"
#define LPM0 _BIS_SR(LPM0_bits) /* Enter Low Power Mode 0 */
#define LPM0_EXIT _BIC_SR_IRQ(LPM0_bits) /* Exit Low Power Mode 0 */
#define LPM1 _BIS_SR(LPM1_bits) /* Enter Low Power Mode 1 */
#define LPM1_EXIT _BIC_SR_IRQ(LPM1_bits) /* Exit Low Power Mode 1 */
#define LPM2 _BIS_SR(LPM2_bits) /* Enter Low Power Mode 2 */
#define LPM2_EXIT _BIC_SR_IRQ(LPM2_bits) /* Exit Low Power Mode 2 */
#define LPM3 _BIS_SR(LPM3_bits) /* Enter Low Power Mode 3 */
#define LPM3_EXIT _BIC_SR_IRQ(LPM3_bits) /* Exit Low Power Mode 3 */
#define LPM4 _BIS_SR(LPM4_bits) /* Enter Low Power Mode 4 */
#define LPM4_EXIT _BIC_SR_IRQ(LPM4_bits) /* Exit Low Power Mode 4 */
#endif /* End #defines for C */
/************************************************************
* PERIPHERAL FILE MAP
************************************************************/
/************************************************************
* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS
************************************************************/
#define IE1_ 0x0000 /* Interrupt Enable 1 */
sfrb(IE1, IE1_);
#define WDTIE (0x01) /* Watchdog Interrupt Enable */
#define OFIE (0x02) /* Osc. Fault Interrupt Enable */
#define NMIIE (0x10) /* NMI Interrupt Enable */
#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */
#define IFG1_ 0x0002 /* Interrupt Flag 1 */
sfrb(IFG1, IFG1_);
#define WDTIFG (0x01) /* Watchdog Interrupt Flag */
#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */
#define PORIFG (0x04) /* Power On Interrupt Flag */
#define RSTIFG (0x08) /* Reset Interrupt Flag */
#define NMIIFG (0x10) /* NMI Interrupt Flag */
/************************************************************
* Basic Clock Module
************************************************************/
#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */
#define DCOCTL_ 0x0056 /* DCO Clock Frequency Control */
sfrb(DCOCTL, DCOCTL_);
#define BCSCTL1_ 0x0057 /* Basic Clock System Control 1 */
sfrb(BCSCTL1, BCSCTL1_);
#define BCSCTL2_ 0x0058 /* Basic Clock System Control 2 */
sfrb(BCSCTL2, BCSCTL2_);
#define BCSCTL3_ 0x0053 /* Basic Clock System Control 3 */
sfrb(BCSCTL3, BCSCTL3_);
#define MOD0 (0x01) /* Modulation Bit 0 */
#define MOD1 (0x02) /* Modulation Bit 1 */
#define MOD2 (0x04) /* Modulation Bit 2 */
#define MOD3 (0x08) /* Modulation Bit 3 */
#define MOD4 (0x10) /* Modulation Bit 4 */
#define DCO0 (0x20) /* DCO Select Bit 0 */
#define DCO1 (0x40) /* DCO Select Bit 1 */
#define DCO2 (0x80) /* DCO Select Bit 2 */
#define RSEL0 (0x01) /* Range Select Bit 0 */
#define RSEL1 (0x02) /* Range Select Bit 1 */
#define RSEL2 (0x04) /* Range Select Bit 2 */
#define RSEL3 (0x08) /* Range Select Bit 3 */
#define DIVA0 (0x10) /* ACLK Divider 0 */
#define DIVA1 (0x20) /* ACLK Divider 1 */
#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */
#define XT2OFF (0x80) /* Enable XT2CLK */
#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */
#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */
#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */
#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */
#define DIVS0 (0x02) /* SMCLK Divider 0 */
#define DIVS1 (0x04) /* SMCLK Divider 1 */
#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */
#define DIVM0 (0x10) /* MCLK Divider 0 */
#define DIVM1 (0x20) /* MCLK Divider 1 */
#define SELM0 (0x40) /* MCLK Source Select 0 */
#define SELM1 (0x80) /* MCLK Source Select 1 */
#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */
#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */
#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */
#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */
#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */
#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */
#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */
#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */
#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */
#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */
#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */
#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */
#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */
#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */
#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */
#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */
#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */
#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */
#define XT2S0 (0x40) /* Mode 0 for XT2 */
#define XT2S1 (0x80) /* Mode 1 for XT2 */
#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */
#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */
#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */
#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */
#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */
#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */
#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */
#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */
#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */
#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */
#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */
#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal */
/************************************************************
* Comparator A
************************************************************/
#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */
#define CACTL1_ 0x0059 /* Comparator A Control 1 */
sfrb(CACTL1, CACTL1_);
#define CACTL2_ 0x005A /* Comparator A Control 2 */
sfrb(CACTL2, CACTL2_);
#define CAPD_ 0x005B /* Comparator A Port Disable */
sfrb(CAPD, CAPD_);
#define CAIFG (0x01) /* Comp. A Interrupt Flag */
#define CAIE (0x02) /* Comp. A Interrupt Enable */
#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */
#define CAON (0x08) /* Comp. A enable */
#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */
#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */
#define CARSEL (0x40) /* Comp. A Internal Reference Enable */
#define CAEX (0x80) /* Comp. A Exchange Inputs */
#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */
#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */
#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */
#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/
#define CAOUT (0x01) /* Comp. A Output */
#define CAF (0x02) /* Comp. A Enable Output Filter */
#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */
#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */
#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */
#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */
#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */
#define CASHORT (0x80) /* Comp. A Short + and - Terminals */
#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */
#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */
#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */
#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */
#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */
#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */
#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */
#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 */
/*************************************************************
* Flash Memory
*************************************************************/
#define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */
#define FCTL1_ 0x0128 /* FLASH Control 1 */
sfrw(FCTL1, FCTL1_);
#define FCTL2_ 0x012A /* FLASH Control 2 */
sfrw(FCTL2, FCTL2_);
#define FCTL3_ 0x012C /* FLASH Control 3 */
sfrw(FCTL3, FCTL3_);
#define FRKEY (0x9600) /* Flash key returned by read */
#define FWKEY (0xA500) /* Flash key for write */
#define FXKEY (0x3300) /* for use with XOR instruction */
#define ERASE (0x0002) /* Enable bit for Flash segment erase */
#define MERAS (0x0004) /* Enable bit for Flash mass erase */
#define WRT (0x0040) /* Enable bit for Flash write */
#define BLKWRT (0x0080) /* Enable bit for Flash segment write */
#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */
#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */
#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */
#ifndef FN2
#define FN2 (0x0004)
#endif
#ifndef FN3
#define FN3 (0x0008)
#endif
#ifndef FN4
#define FN4 (0x0010)
#endif
#define FN5 (0x0020)
#define FSSEL0 (0x0040) /* Flash clock select 0 */ /* to distinguish from USART SSELx */
#define FSSEL1 (0x0080) /* Flash clock select 1 */
#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */
#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */
#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */
#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */
#define BUSY (0x0001) /* Flash busy: 1 */
#define KEYV (0x0002) /* Flash Key violation flag */
#define ACCVIFG (0x0004) /* Flash Access violation flag */
#define WAIT (0x0008) /* Wait flag for segment write */
#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */
#define EMEX (0x0020) /* Flash Emergency Exit */
#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */
#define FAIL (0x0080) /* Last Program or Erase failed */
/************************************************************
* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
************************************************************/
#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
#define P1IN_ 0x0020 /* Port 1 Input */
const_sfrb(P1IN, P1IN_);
#define P1OUT_ 0x0021 /* Port 1 Output */
sfrb(P1OUT, P1OUT_);
#define P1DIR_ 0x0022 /* Port 1 Direction */
sfrb(P1DIR, P1DIR_);
#define P1IFG_ 0x0023 /* Port 1 Interrupt Flag */
sfrb(P1IFG, P1IFG_);
#define P1IES_ 0x0024 /* Port 1 Interrupt Edge Select */
sfrb(P1IES, P1IES_);
#define P1IE_ 0x0025 /* Port 1 Interrupt Enable */
sfrb(P1IE, P1IE_);
#define P1SEL_ 0x0026 /* Port 1 Selection */
sfrb(P1SEL, P1SEL_);
#define P1SEL2_ 0x0041 /* Port 1 Selection 2 */
sfrb(P1SEL2, P1SEL2_);
#define P1REN_ 0x0027 /* Port 1 Resistor Enable */
sfrb(P1REN, P1REN_);
#define P2IN_ 0x0028 /* Port 2 Input */
const_sfrb(P2IN, P2IN_);
#define P2OUT_ 0x0029 /* Port 2 Output */
sfrb(P2OUT, P2OUT_);
#define P2DIR_ 0x002A /* Port 2 Direction */
sfrb(P2DIR, P2DIR_);
#define P2IFG_ 0x002B /* Port 2 Interrupt Flag */
sfrb(P2IFG, P2IFG_);
#define P2IES_ 0x002C /* Port 2 Interrupt Edge Select */
sfrb(P2IES, P2IES_);
#define P2IE_ 0x002D /* Port 2 Interrupt Enable */
sfrb(P2IE, P2IE_);
#define P2SEL_ 0x002E /* Port 2 Selection */
sfrb(P2SEL, P2SEL_);
#define P2SEL2_ 0x0042 /* Port 2 Selection 2 */
sfrb(P2SEL2, P2SEL2_);
#define P2REN_ 0x002F /* Port 2 Resistor Enable */
sfrb(P2REN, P2REN_);
/************************************************************
* Timer0_A3
************************************************************/
#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */
#define TA0IV_ 0x012E /* Timer0_A3 Interrupt Vector Word */
const_sfrw(TA0IV, TA0IV_);
#define TA0CTL_ 0x0160 /* Timer0_A3 Control */
sfrw(TA0CTL, TA0CTL_);
#define TA0CCTL0_ 0x0162 /* Timer0_A3 Capture/Compare Control 0 */
sfrw(TA0CCTL0, TA0CCTL0_);
#define TA0CCTL1_ 0x0164 /* Timer0_A3 Capture/Compare Control 1 */
sfrw(TA0CCTL1, TA0CCTL1_);
#define TA0CCTL2_ 0x0166 /* Timer0_A3 Capture/Compare Control 2 */
sfrw(TA0CCTL2, TA0CCTL2_);
#define TA0R_ 0x0170 /* Timer0_A3 */
sfrw(TA0R, TA0R_);
#define TA0CCR0_ 0x0172 /* Timer0_A3 Capture/Compare 0 */
sfrw(TA0CCR0, TA0CCR0_);
#define TA0CCR1_ 0x0174 /* Timer0_A3 Capture/Compare 1 */
sfrw(TA0CCR1, TA0CCR1_);
#define TA0CCR2_ 0x0176 /* Timer0_A3 Capture/Compare 2 */
sfrw(TA0CCR2, TA0CCR2_);
/* Alternate register names */
#define TAIV TA0IV /* Timer A Interrupt Vector Word */
#define TACTL TA0CTL /* Timer A Control */
#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */
#define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */
#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */
#define TAR TA0R /* Timer A */
#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */
#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */
#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */
#define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */
#define TACTL_ TA0CTL_ /* Timer A Control */
#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */
#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */
#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */
#define TAR_ TA0R_ /* Timer A */
#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */
#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */
#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 */
/* Alternate register names 2 */
#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */
#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */
#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */
#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */
#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */
#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */
#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */
#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */
#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */
#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */
#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */
#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */
#define TASSEL1 (0x0200) /* Timer A clock source select 1 */
#define TASSEL0 (0x0100) /* Timer A clock source select 0 */
#define ID1 (0x0080) /* Timer A clock input divider 1 */
#define ID0 (0x0040) /* Timer A clock input divider 0 */
#define MC1 (0x0020) /* Timer A mode control 1 */
#define MC0 (0x0010) /* Timer A mode control 0 */
#define TACLR (0x0004) /* Timer A counter clear */
#define TAIE (0x0002) /* Timer A counter interrupt enable */
#define TAIFG (0x0001) /* Timer A counter interrupt flag */
#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */
#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
#define MC_2 (0x0020) /* Timer A mode control: 2 - Continous up */
#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */
#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */
#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */
#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */
#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */
#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */
#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */
#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */
#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */
#define CM1 (0x8000) /* Capture mode 1 */
#define CM0 (0x4000) /* Capture mode 0 */
#define CCIS1 (0x2000) /* Capture input select 1 */
#define CCIS0 (0x1000) /* Capture input select 0 */
#define SCS (0x0800) /* Capture sychronize */
#define SCCI (0x0400) /* Latched capture signal (read) */
#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
#define OUTMOD2 (0x0080) /* Output mode 2 */
#define OUTMOD1 (0x0040) /* Output mode 1 */
#define OUTMOD0 (0x0020) /* Output mode 0 */
#define CCIE (0x0010) /* Capture/compare interrupt enable */
#define CCI (0x0008) /* Capture input signal (read) */
#define OUT (0x0004) /* PWM Output signal if output mode 0 */
#define COV (0x0002) /* Capture/compare overflow flag */
#define CCIFG (0x0001) /* Capture/compare interrupt flag */
#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */
#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */
#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */
#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */
#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */
#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */
#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */
#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */
#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */
#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */
#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */
#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */
#define CM_0 (0x0000) /* Capture mode: 0 - disabled */
#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */
#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */
#define CM_3 (0xC000) /* Capture mode: 1 - both edges */
/* T0_A3IV Definitions */
#define TA0IV_NONE (0x0000) /* No Interrupt pending */
#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
#define TA0IV_6 (0x0006) /* Reserved */
#define TA0IV_8 (0x0008) /* Reserved */
#define TA0IV_TAIFG (0x000A) /* TA0IFG */
/************************************************************
* USI
************************************************************/
#define __MSP430_HAS_USI__ /* Definition to show that Module is available */
#define USICTL0_ 0x0078 /* USI Control Register 0 */
sfrb(USICTL0, USICTL0_);
#define USICTL1_ 0x0079 /* USI Control Register 1 */
sfrb(USICTL1, USICTL1_);
#define USICKCTL_ 0x007A /* USI Clock Control Register */
sfrb(USICKCTL, USICKCTL_);
#define USICNT_ 0x007B /* USI Bit Counter Register */
sfrb(USICNT, USICNT_);
#define USISRL_ 0x007C /* USI Low Byte Shift Register */
sfrb(USISRL, USISRL_);
#define USISRH_ 0x007D /* USI High Byte Shift Register */
sfrb(USISRH, USISRH_);
#define USICTL_ 0x0078 /* USI Control Register */
sfrw(USICTL, USICTL_);
#define USICCTL_ 0x007A /* USI Clock and Counter Control Register */
sfrw(USICCTL, USICCTL_);
#define USISR_ 0x007C /* USI Shift Register */
sfrw(USISR, USISR_);
#define USIPE7 (0x80) /* USI Port Enable Px.7 */
#define USIPE6 (0x40) /* USI Port Enable Px.6 */
#define USIPE5 (0x20) /* USI Port Enable Px.5 */
#define USILSB (0x10) /* USI LSB first 1:LSB / 0:MSB */
#define USIMST (0x08) /* USI Master Select 0:Slave / 1:Master */
#define USIGE (0x04) /* USI General Output Enable Latch */
#define USIOE (0x02) /* USI Output Enable */
#define USISWRST (0x01) /* USI Software Reset */
#define USICKPH (0x80) /* USI Sync. Mode: Clock Phase */
#define USII2C (0x40) /* USI I2C Mode */
#define USISTTIE (0x20) /* USI START Condition interrupt enable */
#define USIIE (0x10) /* USI Counter Interrupt enable */
#define USIAL (0x08) /* USI Arbitration Lost */
#define USISTP (0x04) /* USI STOP Condition received */
#define USISTTIFG (0x02) /* USI START Condition interrupt Flag */
#define USIIFG (0x01) /* USI Counter Interrupt Flag */
#define USIDIV2 (0x80) /* USI Clock Divider 2 */
#define USIDIV1 (0x40) /* USI Clock Divider 1 */
#define USIDIV0 (0x20) /* USI Clock Divider 0 */
#define USISSEL2 (0x10) /* USI Clock Source Select 2 */
#define USISSEL1 (0x08) /* USI Clock Source Select 1 */
#define USISSEL0 (0x04) /* USI Clock Source Select 0 */
#define USICKPL (0x02) /* USI Clock Polarity 0:Inactive=Low / 1:Inactive=High */
#define USISWCLK (0x01) /* USI Software Clock */
#define USIDIV_0 (0x00) /* USI Clock Divider: 0 */
#define USIDIV_1 (0x20) /* USI Clock Divider: 1 */
#define USIDIV_2 (0x40) /* USI Clock Divider: 2 */
#define USIDIV_3 (0x60) /* USI Clock Divider: 3 */
#define USIDIV_4 (0x80) /* USI Clock Divider: 4 */
#define USIDIV_5 (0xA0) /* USI Clock Divider: 5 */
#define USIDIV_6 (0xC0) /* USI Clock Divider: 6 */
#define USIDIV_7 (0xE0) /* USI Clock Divider: 7 */
#define USISSEL_0 (0x00) /* USI Clock Source: 0 */
#define USISSEL_1 (0x04) /* USI Clock Source: 1 */
#define USISSEL_2 (0x08) /* USI Clock Source: 2 */
#define USISSEL_3 (0x0C) /* USI Clock Source: 3 */
#define USISSEL_4 (0x10) /* USI Clock Source: 4 */
#define USISSEL_5 (0x14) /* USI Clock Source: 5 */
#define USISSEL_6 (0x18) /* USI Clock Source: 6 */
#define USISSEL_7 (0x1C) /* USI Clock Source: 7 */
#define USISCLREL (0x80) /* USI SCL Released */
#define USI16B (0x40) /* USI 16 Bit Shift Register Enable */
#define USIIFGCC (0x20) /* USI Interrupt Flag Clear Control */
#define USICNT4 (0x10) /* USI Bit Count 4 */
#define USICNT3 (0x08) /* USI Bit Count 3 */
#define USICNT2 (0x04) /* USI Bit Count 2 */
#define USICNT1 (0x02) /* USI Bit Count 1 */
#define USICNT0 (0x01) /* USI Bit Count 0 */
/************************************************************
* WATCHDOG TIMER
************************************************************/
#define __MSP430_HAS_WDT__ /* Definition to show that Module is available */
#define WDTCTL_ 0x0120 /* Watchdog Timer Control */
sfrw(WDTCTL, WDTCTL_);
/* The bit names have been prefixed with "WDT" */
#define WDTIS0 (0x0001)
#define WDTIS1 (0x0002)
#define WDTSSEL (0x0004)
#define WDTCNTCL (0x0008)
#define WDTTMSEL (0x0010)
#define WDTNMI (0x0020)
#define WDTNMIES (0x0040)
#define WDTHOLD (0x0080)
#define WDTPW (0x5A00)
/* WDT-interval times [1ms] coded with Bits 0-2 */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL) /* 32ms interval (default) */
#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0) /* 8ms " */
#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1) /* 0.5ms " */
#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL) /* 1000ms " */
#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
/* Watchdog mode -> reset after expired time */
/* WDT is clocked by fSMCLK (assumed 1MHz) */
#define WDT_MRST_32 (WDTPW+WDTCNTCL) /* 32ms interval (default) */
#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS0) /* 8ms " */
#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS1) /* 0.5ms " */
#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS1+WDTIS0) /* 0.064ms " */
/* WDT is clocked by fACLK (assumed 32KHz) */
#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL) /* 1000ms " */
#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS0) /* 250ms " */
#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1) /* 16ms " */
#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0) /* 1.9ms " */
/* INTERRUPT CONTROL */
/* These two bits are defined in the Special Function Registers */
/* #define WDTIE 0x01 */
/* #define WDTIFG 0x01 */
/************************************************************
* Calibration Data in Info Mem
************************************************************/
#ifndef __DisableCalData
#define CALDCO_16MHZ_ 0x10F8 /* DCOCTL Calibration Data for 16MHz */
const_sfrb(CALDCO_16MHZ, CALDCO_16MHZ_);
#define CALBC1_16MHZ_ 0x10F9 /* BCSCTL1 Calibration Data for 16MHz */
const_sfrb(CALBC1_16MHZ, CALBC1_16MHZ_);
#define CALDCO_12MHZ_ 0x10FA /* DCOCTL Calibration Data for 12MHz */
const_sfrb(CALDCO_12MHZ, CALDCO_12MHZ_);
#define CALBC1_12MHZ_ 0x10FB /* BCSCTL1 Calibration Data for 12MHz */
const_sfrb(CALBC1_12MHZ, CALBC1_12MHZ_);
#define CALDCO_8MHZ_ 0x10FC /* DCOCTL Calibration Data for 8MHz */
const_sfrb(CALDCO_8MHZ, CALDCO_8MHZ_);
#define CALBC1_8MHZ_ 0x10FD /* BCSCTL1 Calibration Data for 8MHz */
const_sfrb(CALBC1_8MHZ, CALBC1_8MHZ_);
#define CALDCO_1MHZ_ 0x10FE /* DCOCTL Calibration Data for 1MHz */
const_sfrb(CALDCO_1MHZ, CALDCO_1MHZ_);
#define CALBC1_1MHZ_ 0x10FF /* BCSCTL1 Calibration Data for 1MHz */
const_sfrb(CALBC1_1MHZ, CALBC1_1MHZ_);
#endif /* #ifndef __DisableCalData */
/************************************************************
* Interrupt Vectors (offset from 0xFFE0)
************************************************************/
#define PORT1_VECTOR (0x0004) /* 0xFFE4 Port 1 */
#define PORT2_VECTOR (0x0006) /* 0xFFE6 Port 2 */
#define USI_VECTOR (0x0008) /* 0xFFE8 USI */
#define TIMER0_A1_VECTOR (0x0010) /* 0xFFF0 Timer0_A CC1, TA */
#define TIMER0_A0_VECTOR (0x0012) /* 0xFFF2 Timer0_A CC0 */
#define WDT_VECTOR (0x0014) /* 0xFFF4 Watchdog Timer */
#define COMPARATORA_VECTOR (0x0016) /* 0xFFF6 Comparator A */
#define NMI_VECTOR (0x001C) /* 0xFFFC Non-maskable */
#define RESET_VECTOR (0x001E) /* 0xFFFE Reset [Highest Priority] */
/************************************************************
* End of Modules
************************************************************/
#ifdef __cplusplus
}
#endif /* extern "C" */
#endif /* #ifndef __MSP430G2112 */
|